Abstract: PROBLEM TO BE SOLVED: To improve the stability and PSRR characteristic of an internal compensating type PMOS low dropout voltage regulator. SOLUTION: A non-inverting variable gain amplifier stage 202 is used for this voltage regulator 200. The gain of the non-inverting variable gain amplifier stage is regulated according to the load current carried in a power PMOS device 206 so as to increase the gain according to the reduction in load current, and the second pole of the voltage regulator 200 is pushed up to the unit gain frequency or more of the voltage regulator. The gain of the non-inverting variable gain amplifier 202 is regulated according to the load current carried in the power PMOS device 206 so as to reduce the gain according to the increase in load current, and the unit gain band width of a loop formed in a compensating capacitor 208 is substantially kept constant.

Abstract: The idea of pole-region assignment is extended to interval gain and phase margin assignment. The internal model control proportional-integral-derivative (IMC-PID) design is examined from the frequency domain point of view. Equations for typical frequency domain specifications such as gain margin, phase margin and bandwidth are derived for the IMC-PID design. The gain and phase margins are monitored in real time and a self-tuning controller with interval gain and phase margin assignment is proposed. An implementation example in the laboratory is also given.

Abstract: A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output NMOS pass device. The voltage regulator uses an inverting inter-stage variable gain amplifier to adjust its gain in response to a load current passing through the output NMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The inverting inter-stage variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power NMOS device such that as the load current increases, the gain decreases, wherein the unity gain bandwidth associated with the loop formed by a compensation capacitor is kept substantially constant.

Abstract: This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-/spl mu/m CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering pole, leading to a nearly 90/spl deg/ phase margin which minimizes input jitter peaking and transient locking overshoot. The PLL damping factor is made insensitive to process variations by making it dependent only upon a bandgap voltage and ratios of circuit elements. This ensures tracking between the natural frequency and the stabilizing zero. The PLL has a frequency range of 125-1250 MHz, frequency resolution better than 500 kHz, and rms jitter less than 0.9% of the oscillator period.

Abstract: A base band circuit forms a part of an automatic gain controller incorporated in a direct conversion receiver, and includes a series of variable gain amplifiers controlled by a gain controller and a feedback loop connected between the output node and the input node of the series of variable gain amplifiers, wherein the feedback loop has an attenuation circuit connected between the output node of the series of variable gain amplifiers and an inverted integrating circuit which, in turn, is connected through an adder and a low pass filter to the input node of the series of variable gain amplifiers so that direct current offset voltage is eliminated from the output signal of the series of variable gain amplifiers without change of cut-off frequency.

Abstract: The spectral shape of a communication signal is preserved by filtering it into a selected number of frequency band signals representing a selected number of the frequency bands. A calculator generates a plurality of initial gain signals having initial gain values for altering the gain of the frequency band signals. Each initial gain signal corresponds to one of the frequency band signals. Each initial gain value is derived from a measurement of the power of at least a portion of one of the frequency band signals. The calculator also generates a plurality of modified gain signals having modified gain values. Each modified gain signal corresponds to at least one of the frequency band signals and each modified gain value is derived from one or more functions of at least two of the initial gain values. The frequency band signals are altered in response to the modified gain signals to generate weighted frequency band signals which are combined to generate an improved communication signal.

Abstract: Techniques to linearly (in dB) adjust the gains of variable gain elements (i.e., variable gain amplifiers or VGAs) in a receiver of transmitter. An input control signal is provided to a conditioning circuit that conditions the control signal to achieve various signal characteristics. The input control signal is limited to within a particular range of values, temperature compensated, scaled (or normalized) to the supply voltages, shifted with an offset, or manipulated in other fashions. The conditioned signal is then provided to an input stage of a linearizer that generates a set of exponentially related signals. This is achieved using, for example, a differential amplifier in which the conditioned control signal is applied to the inputs of the differential amplifier and the collector currents from the differential amplifier comprises the exponentially related signals. An output stage within the linearizer receives the exponentially related signals and, in response, generates a gain control signal. By approximately matching the output stage to a gain stage of the variable gain element and by using the gain control signal generated by output stage, the gain transfer function of the VGA approximates that of the exponentially related signals.

Abstract: This paper proposes an optimization based control scheme for a dual-stage hard disk drive servo system to maximize the tracking accuracy given the actuator bandwidth limitations without knowing the mechanical disturbance model. We proposed to add an outer loop, selected based on optimization of the Youla parameters, to the usual dual-stage controller for tracking accuracy improvement. The Youla parameters are bounded based on specifications of minimum bandwidth, phase margin, and gain margin, and maximum bandwidth limitations. Time domain and frequency domain simulations were performed to show the effectiveness of the design. The tracking accuracy with respect to various noise and disturbance levels was considered. The results suggested that for the noise and disturbance model considered, the mechanical disturbance must be reduced considerably to achieve higher TPI.

Abstract: In a burst-mode, high-speed spread-spectrum communications system, faster convergence of a receiver's automatic gain control (AGC) circuit reduces the time required to bring a received signal within the operating range of an operation amplifier and other radio-frequency and digital sections of the receiving system. A gain control circuit includes a coarse-gain feedback loop and a fine-gain feedback loop to improve convergence speed and at the same time maintain the stability of the AGC circuit. The coarse-gain feedback loop quickly brings the received signal, using a large gain signal, to the desired operating range. The fine-gain feedback loop uses a smaller gain signal to gradually smooth the received signal to avoid saturation on the A/D converters.

Abstract: An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.

Abstract: A soft limiter for a signal processor includes a variable-gain amplifier, and a threshold detector. The variable-gain amplifier includes a signal input for receiving an input signal, a signal output for providing an output signal representative of the input signal, and a gain control input for controlling a gain of the amplifier. The threshold detector is coupled to the gain control input, and includes a control input for receiving a control variable thereon. The threshold detector is configured to set the gain of the amplifier to a first gain value when the control variable exceeds a threshold value, and to set the gain to a second gain value different from the first gain value when the control variable is less than the threshold value.

Abstract: An automatic gain control technique is disclosed for adjusting the gain of an IF amplifier in a communication system, such as an OFDM or DMT communication system. The gain of an RF amplifier is controlled by a known RF automatic gain control circuit that generates an RF gain value. The disclosed IF automatic gain control (AGC) circuit controls the gain of an IF amplifier in the receiver. The disclosed IF AGC monitors the RF gain value, as well as pre-FFT and post-FFT signal energy measurements performed before and after a fast Fourier transform (FFT) stage, respectively, to maintain a desired set point. The IF AGC adjusts the previous IF gain value by an amount opposite to the adjusted RF gain value, if any. If there is no RF gain adjustment, then the IF AGC will adjust the IF gain based on thresholds established for the pre-FFT and post-FFT measurements. If the pre-FFT measurement is within a desired tolerance of the pre-FFT threshold, then the IF gain will be lowered in stepped increments. Otherwise, the IF gain adjustment is the minimum of the difference between (i) the pre-FFT measurement and its threshold, or (ii) the post-FFT measurement and its threshold, multiplied by a loop gain constant.

Abstract: A variable gain amplifier device controlled by a first gain control signal comprises a gain controlled amplifier having a gain and including a differential pair of first and second MOS type transistors configured to operate in a weak inversion region; and a control signal converter configured to convert the first gain control signal into a second gain control signal, and supply the second gain control signal to the gain controlled amplifier to exponentially vary the gain with respect to the first gain control signal.

Abstract: In a gain control device for packet signal receiver, a variable gain amplifier amplifies an input signal with a gain corresponding to a control voltage applied thereto, and a power detector detects output power of the variable gain amplifier. A packet detection circuit detects a packet signal based on the detected output power. A control circuit outputs the control voltage variable with the detected output power, and the control voltage is provided for the amplifier. Thus high-speed gain control is performed immediately after the start of detection of the packet signal. When the elapsed time after the start of detection of the packet signal exceeds a predetermined time, a sample-hold circuit sample-and-holds the control voltage. This control voltage is provided for the amplifier up to the end of reception of the packet signal thereafter. Thus low-speed gain control is performed to provide stable power without distorting the signal wave.

Abstract: An optical device for dynamic gain adjusting includes a dynamic gain adjusting filter having one or more semiconductor optical amplifiers. The dynamic gain adjusting filter may allow dynamically-adjustable spectral gain characteristics. A dynamic gain adjusting filter may be part of an amplifier module or other optical device module, or as an optical module itself. The dynamic gain adjusting filter may be used to reduce gain ripple, control gain tilt, and/or compensate for other gain variations. The one or more semiconductor optical amplifiers of the dynamic gain adjusting filter may be designed and/or controlled to produce different gain profiles. For example, the active region of the semiconductor optical device may comprise several subregions having different structures, dimensions, and/or doping characteristics.

Abstract: Stability analysis and design of an automatic frequency control (AFC) system for in vivo continuous-wave EPR spectroscopy is described. The open-loop function of the feedback control system for the AFC was derived and the stability of the feedback loop systematically examined. A stability analysis of the system is demonstrated and a systematic design procedure is proposed. The design is started from the required system specifications (phase margin, steady-state error, and system bandwidth) and clear guidelines for designing an AFC system are given. A case study of the design is presented based on the specific needs of in vivo EPR measurements. A phase margin of 53 degrees, a steady-state error of 1.6%, and a system bandwidth of up to 1.8 kHz were obtained in the designed AFC system. The system specifications defined in advance are satisfied in this case study.

Abstract: High performance operational transconductance amplifier (OTA) structures for high-speed, low-voltage, switched-capacitor (SC) based sigma-delta modulator applications have been designed utilizing an efficient circuit optimization strategy presented in this paper. The main idea is to use external programs together with a circuit optimizer to construct flexible optimization algorithms. Optimization goals and constraints are derived from analytical equations and application requirements. Using a 0.35 /spl mu/m CMOS processing technology a complementary folded cascode feedforward compensated (CFCFC) OTA with 2.5 V supply obtained 470 MHz unity-gain frequency, 350 V//spl mu/s slew rate, over 74 dB gain, and over 70/spl deg/ phase margin using 10 pF load capacitances. The optimization strategy was verified by measuring fabricated CFCFC OTA and sigma-delta modulator. The measurement results demonstrate a good agreement with the simulations.

Abstract: PROBLEM TO BE SOLVED: To estimate the pole phase at a high speed without using an FFT while reducing estimation phase error due to noise in the control of a PM motor. SOLUTION: An integrator 21 and a high frequency voltage generating section 22 obtain a sinusoidal single oscillation high frequency voltage from a high frequency angular speed command and the high frequency voltage is injected to the voltage command of dc-axis. High frequency extracting sections 23 and 24 extract the high frequency current component contained in the dc-axis and qc-axis currents. A positive phase map operating section 25 and a negative phase map operating section 26 obtain the maps for the positive phase axis and the negative phase axis of the high frequency current component thus extracted. A positive/negative phase asymmetry extracting section 27 obtains the asymmetry of two maps as a feature amount. A phase estimating section 28 determines an estimated phase θc from the feature amount.

Abstract: An automatic gain controller has variable gain amplifiers (11a), (11b) for variably amplifying the input signals (RI1), (RI2) and a control loop that respectively performs automatic gain control of these variable gain amplifiers (11a), (11b) via feedback control of the output signal level. Variation amount in the detected output of the demodulated outputs (RD1), (RD2) is detected in the variation amount detector (20) . The control section (19) selects the control loop where the output signal level is the highest when the variation amount is small and the system is in the stable state, and performs automatic gain control via a gain control signal in this control loop and correction gain control signals in the other control loops, and places in the non-operating state the gain control signal generator of the other control loops.

Abstract: An iterative procedure for achieving gain and phase margin specifications for a PI controller is presented The iteration scheme is based on the use of two relay tests applied to the closed loop system The first relay test is standard and it is used here to obtain the gain margin of the closed loop system at each iteration step The second one is applied to the closed loop system such that a limit cycle is developed at the loop gain crossover frequency Under this condition it is possible to obtain an estimate of the phase margin of the loop transfer function The procedure is applied to a PI controller tuning in a heat exchanger in laboratory scale using desired gain and phase margin specifications

Abstract: This paper will discuss the design of PI and PID controller tuning rules to compensate processes with delay, that are modelled in a number of ways. The rules allow the achieveme nt of constant gain and phase margins as the delay varies.

Abstract: This paper concerns disturbance observer design for a direct drive tape transport servo system. A gain-scheduled notch filter is used in the outer-loop controller design for the decoupled tension loop to cancel a lightly-damped resonance. The disturbance observer is used to attenuate the effects of both stiction during start-up and the periodic disturbances caused by reel eccentricities during steady running. This paper presents the sensitivity function analysis by transforming overall system into an equivalent loop gain with both feedforward compensator and feedback compensator. Contrary to common approximation used in disturbance observer, this analysis shows that the outer-loop controller could be adversely affected by the introduction of disturbance observer. The analysis also shows that noise is amplified by the introduction of the disturbance observer. For the tape transport servo design, the location of the notch is shifted by the introduction of the disturbance observer, Which results in small phase margin. The loop gain analysis also provides an insight for the disturbance observer filter selection for the tape transport servo system. Experimental data show the effectiveness of the new design.

Abstract: In an automatic gain control amplifier, an RF automatic gain controller controls the gain of a radio frequency signal. A frequency converter frequency-converts the radio frequency signal into an intermediate frequency signal. An IF automatic gain controller controls the gain of the intermediate frequency. A level detector detects a signal level of the gain-controlled intermediate frequency signal, and generates a level signal. An automatic gain control signal generator separately controls, based the level signal, the RF automatic gain controller and the IF automatic gain controller.

Abstract: The gain of a variable gain amplifier (20) is arranged to amplify electrical signals output from a fiber optic gyroscope (12) is controlled to provides a stable AGC response irrespective of the actual gain level. A perturbation injection circuit (14) provides a perturbation signal ±d to a phase modulator (16) connected to the fiber optic gyro (12). A perturbation compensation circuit (24) applies perturbation compensation signals to signals output from the variable gain amplifier (20) and produces a compensated signal by reducing the magnitude of the perturbation in the amplified signal output from the variable gain amplifier (20). A gain error circuit (28) connected to the perturbation signal remaining in the amplified signal after perturbation compensation. A feedback system (32, 34) provides a gain control signal to the variable gain amplifier (20) to reduce the magnitude of the gain error signal.

Abstract: A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up mode signal controls electronics associated with one or more amplifiers to facilitate settling time of an output signal of the amplifier(s) that occurs when the gain of the amplifier changes. The gain control signal also can be delayed to provide a delayed version of the gain control signal for controlling gain of the amplifier(s).

Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.

Abstract: A feedback circuit has an optical coupler with a feedback gain control. The feedback gain control includes an active element connected to vary current flow depending on changes in gain of the optical coupler.

Abstract: A transmitter has a quadrature modulator that provides a modulated signal at a first frequency. The transmitter has a phase locked loop, of which a voltage controlled oscillator is coupled after the phase comparator of the phase locked loop, and further has a power amplifier in the transmit signal path of the transmitter. The phase locked loop further has a down-converter in the feedback path, from the output of the power amplifier, and a feedback input to the phase comparator. The transmitter further has an amplitude restoration arrangement, that restores amplitude information contained in the feedback signal provided by the down-converter. In operation, the phase locked loop replicates, at the carrier frequency, angle information contained in the quadrature modulated signal, and the amplitude restoration arrangement controls the gain of the transmit power amplifier such that input signals at the phase comparator substantially are equal.

Abstract: A gain control for a phase locked loop circuit is provided. In the phase-locked loop circuit, a voltage controlled oscillator generates a reference signal responsive to the level of a tuning voltage. A phase detector generates the tuning voltage update, which is indicative of a phase relationship between the reference signal and an input signal. A feedback circuit detects the tuning voltage and generates an adjustment signal in response. The adjustment signal is then used to adjust the loop gain at any specific tuning voltage. In a specific example, the adjustment signal is used to adjust the current gain of the phase detector in a manner that is complementary to the non-linear voltage gain of the voltage-controlled oscillator.