About: Phase-locked loop is a research topic. Over the lifetime, 35976 publications have been published within this topic receiving 369935 citations. The topic is also known as: PLL.
TL;DR: In this article, a decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL) was proposed to detect the fundamental-frequency positive-sequence component of the utility voltage under unbalanced and distorted conditions.
Abstract: This paper deals with a crucial aspect in the control of grid-connected power converters, i.e., the detection of the fundamental-frequency positive-sequence component of the utility voltage under unbalanced and distorted conditions. Specifically, it proposes a positive-sequence detector based on a new decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL), which completely eliminates the detection errors of conventional synchronous reference frame PLL's (SRF-PLL). This is achieved by transforming both positive- and negative-sequence components of the utility voltage into the double SRF, from which a decoupling network is developed in order to cleanly extract and separate the positive- and negative-sequence components. The resultant DDSRF-PLL conducts then to a fast, precise, and robust positive-sequence voltage detection even under unbalanced and distorted grid conditions. The paper presents a detailed description and derivation of the proposed detection method, together with an extensive evaluation using simulation and experimental results from a digital signal processor-based laboratory prototype in order to verify and validate the excellent performance achieved by the DDSRF-PLL
TL;DR: In this paper, an identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction, and the behavior of phase-locked oscillators under injection pulling is also formulated.
Abstract: Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.
TL;DR: In this article, the phase tracking system of the three phase utility interface inverters is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system.
Abstract: The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the three phase utility interface inverters. The dynamic behavior of the closed loop PLL system is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system. In particular, the performance of the three phase PLL system is analyzed in the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by the nonlinear load conditions and measurement errors. The tracking errors under these distorted utility conditions are also derived. The phase tracking system is implemented in a digital manner using a digital signal processor (DSP) to verify the analytic results. The design considerations for the phase tracking system are deduced from the analytic and experimental results.
TL;DR: In this article, a phase-locked-loop (PLL) method for single-phase systems was proposed to detect the phase angle, amplitude and frequency of the utility voltage.
Abstract: Phase, amplitude and frequency of the utility voltage are critical information for the operation of the grid-connected inverter systems. In such applications, an accurate and fast detection of the phase angle, amplotude and frequency of the utility voltage is essential to assure the correct generation of the reference signals and to cope with the new upcoming standards. This paper presents a new phase-locked-loop (PLL) method for single-phase systems. The novelty consists in generating the orthogonal voltage system using a structure based on second order generalized integrator (SOGI). The proposed structure has the following advantages: — it has a simple implementation; — the generated orthogonal system is filtered without delay by the same structure due to its resonance at the fundamental frequency, — the proposed structure is not affected by the frequency changes. The solutions for the discrete implementation of the new proposed structure are also presented. Experimental results validate the effectiveness of the proposed method.
TL;DR: In this article, the small-signal impedance of three-phase grid-tied inverters with feedback control and phase-locked loop (PLL) in the synchronous reference ( d-q ) frame is analyzed.
Abstract: This paper analyzes the small-signal impedance of three-phase grid-tied inverters with feedback control and phase-locked loop (PLL) in the synchronous reference ( d-q ) frame. The result unveils an interesting and important feature of three-phase grid-tied inverters – namely, that its q–q channel impedance behaves as a negative incremental resistor. Moreover, this paper shows that this behavior is a consequence of grid synchronization, where the bandwidth of the PLL determines the frequency range of the resistor behavior, and the power rating of the inverter determines the magnitude of the resistor. Advanced PLL, current, and power control strategies do not change this feature. An example shows that under weak grid conditions, a change of the PLL bandwidth could lead the inverter system to unstable conditions as a result of this behavior. Harmonic resonance and instability issues can be analyzed using the proposed impedance model. Simulation and experimental measurements verify the analysis.