Abstract: We focus on the robust joint design of the transmit waveform and filtering structure for polarimetric radar. Considering the worst case signal-to-interference plus noise ratio (SINR) at the output as the figure of merit to optimize under both a similarity and an energy constraint on the transmit signal, we develop an iterative optimization procedure. The effectiveness of the proposed method is validated through experimental results, underlining the performance improvement given by a full-polarimetric design.

Abstract: This study introduces the use of model predictive control (MPC) to improve the performance of pre-compensated power supplies, and in particular of DC-DC converters, by dynamically modifying their output voltage reference. The importance of developing controllers for pre-compensated converters is twofold. First, the hierarchical structure is particularly useful when the primal controller is already coded, or hardware based, and cannot be changed. Second, the double-loop and, possible, multi-rate structure represents a computationally cheaper alternative to a direct MPC that would replace the primal controller and would require a much higher sampling frequency. In this study a MPC controller has been applied for the regulation of a pre-compensated synchronous DC-DC buck converter. The aim is to improve the performance of standard voltage mode control (VMC), without replacing the linear controller and without drastically affecting the computational burden. The algorithm has been tested both in simulation and experimentally, on commercially available hardware. The results show the performance improvement with respect to the standard VMC, as well as the feasibility of the proposed approach in an embedded platform. Tests with different primal controller tunings, and unknown varying loads, confirm the advantages of the method.

Abstract: With CMOS scaling beyond 14 nm, reliability is a major concern for IC manufacturers. Reliability-aware design has a non-negligible overhead and cannot account for user experience in mobile devices. An alternative is dynamic reliability management (DRM), which counteracts degradation by adapting the operating conditions at runtime. In this paper, for the first time we formulate DRM as an optimization problem that accounts for reliability, temperature and performance. We develop an optimal policy for multicores using convex optimization, and show that it is not feasible to implement on real systems. For this reason, we propose workload-aware reliability management (WARM), a fast DRM technique adapting to diverse workload requirements to trade reliability and user experience. WARM is implemented and tested on a real Android device. WARM approximates the solution of the convex solver within 5% on average, while executing more than $400 {\times }$ faster. WARM integrates a thermal controller that allocates tasks to meet thermal constraints. This is required since degradation strongly depends on temperature. We show that WARM meets temperature constraints within 5% in 87.5% more cases than the state-of-the-art. We show that WARM task allocation achieves up to one year lifetime improvement for a multicore platform. It can achieve up to 100% of performance improvement on cluster architectures, such as big.LITTLE, while still guaranteeing the reliability target. Finally, we show that it achieves performance in the 4% of the maximum for a broad range of a applications, while meeting the reliability constraints.

Abstract: In the present scenario, performance evaluation of employees in industries is done manually, in which there are ample chances of biases. It is observed that manual employee evaluation systems can be efficiently eliminated by using ubiquitous sensing capabilities of Internet of things (IoT) devices to monitor industrial employees. However, none of the authors have used IoT data for automating performance evaluation systems of employees. Hence, this paper proposes a game theoretic approach for an IoT-based employee performance evaluation in industry. The system infers useful results about the performance of employees by mining data collected by the sensory nodes using the MapReduce model. The information hence obtained is then used to draw automated decisions for employees using game theory. The system is analyzed both experimentally and mathematically. The experimental evaluation compares the proposed system with other techniques of data mining and decision making. The results depict that the proposed system evaluates the performance of employees efficiently and shows a performance improvement over other techniques. The mathematical evaluation shows that correct evaluation of employees by the system effectively motivates employees in favor of the industry. Thus, the proposed system effectively and efficiently automates the employee evaluation system and decision-making process in the industry.

Abstract: This paper presents a calibration method of a rule-based energy management strategy designed for a plug-in hybrid electric vehicle, which aims to find the optimal set of control parameters to compromise within the conflicting calibration requirements (e.g. emissions and economy). A comprehensive evaluating indicator covering emissions and economy performance is constructed by the method of radar chart. Moreover, a radial basis functions (RBFs) neural network model is proposed to establish a precise model within the control parameters and the comprehensive evaluation indicator. The best set of control parameters under offline calibration is gained by the multi-island genetic algorithm. Finally, the offline calibration results are compared with the experimental results using a chassis dynamometer. The comparison results validate the effectiveness of the proposed offline calibrating approach, which is based on the radar chart method and the RBF neural network model on vehicle performance improvement and calibrating efficiency.

Abstract: Energy consumption is a key concern in the deployment and operation of current data networks, for which software-defined networks (SDNs) have become a promising alternative. Although several works have been proposed to improve the energy efficiency, these techniques may lead to performance degradations when QoS requirements are neglected. Inspired by this problem, this letter introduces a new routing strategy, jointly considering QoS requirements and energy awareness in SDN with in-band control traffic. To that end, we present a complete formulation of the optimization problem and implement a multi-objective evolutionary algorithm. Simulation results validate the performance improvement on critical network parameters.

Abstract: Servo system is widely used in NC machines and its performance directly determines the precision of the machines. In most situations, the control structure for the servo system usually contains a cascaded P-PI feedback controller and a feedforward controller. This paper focuses on the feedforward controller parameters tuning to improve the servo performance. The feedforward controller consists of a model inversion and a parameterized disturbance model. Its parameters are tuned iteratively using the last cycle motion results. This method has the good extrapolation capability to the references and the performance improvement capacity. Moreover, it is easy to implement in real machines due to the simplicity and thus is of interest to control engineers. Experiments are carried out on an industrial prototype system. The results show that the proposed tuning method can improve the servo performance rapidly and the references are not required to keep the same during the tuning process.

Abstract: Performance investigation of Active Power Filter for harmonic elimination is annterdisciplinary area of interest for many researchers.This paper presents performance improvement of 3-phase Series Active Power Filter (SeAPF) with Hysteresis Current Control technique for elimination of harmonic in a 3-phase distribution system. The shunt active filter employs a simple method called synchronous detection technique for reference current generation. proportional-integral (PI) and Fuzzy Logic Controller (FLC) are designed to adjust the parameters of the SePF system. The proposed system has achieved a low Total Harmonic Distortion (THD) which demonstrates the effectiveness of the presented method. This paper presents B4inverter topology which give reduced number of switches and switching losses. The simulation of global system control and power circuits is performed using Matlab- Simulink and Sim Power System toolbox. The simulation results presented demonstrate improved performance of the SePF system with the proposed fuzzy logic control approach.

Abstract: The coming 5G cellular communication system is envisioned to support a wide range of new use cases on top of regular cellular mobile broadband services. One of the 5G usage scenarios is ultra-reliable low-latency communications (URLLC). It has been predicted that URLLC will play an essential role in enabling wireless communications for emerging new services and applications such as factory automation, remote manipulation, autonomous driving and tactile Internet, to name a few. The two key performance metrics related to URLLC are latency and reliability. In this paper three coordinated multi-cell resource allocation methods for 5G URLLC are presented in a typical indoor environment. From the simulation results, it can be observed that handling inter-cell interference effectively can lead to a significant performance improvement in terms of reliability without bringing any degradation to the latency performance.

Abstract: In network-on-chip (NoC)-based systems, performance enhancement has primarily focused on the network itself, with little attention paid on controlling traffic injection at the network boundary. This is unsatisfactory because traffic may be over injected, aggravating congestion, and lowering performance. Recently, traffic regulation is proposed as an orthogonal means for performance improvement. Rather than as soon as possible admission, traffic regulation may hold back packet injection by admitting packets into the network only when the accumulated traffic volume at any time interval does not exceed a threshold. These regulation techniques are, however, often static, likely causing overregulation and underregulation. We propose dynamic traffic regulation to improve the system performance for NoC-based multi/many-processor systems-on-chip (MPSoC) and chip multi/many-core processor (CMP) designs. It can be applied to MPSoCs for intellectual property integration in an open-loop fashion by injecting traffic according to its run-time profiled characteristics. It can also be applied to CMPs in a closed-loop fashion by admitting traffic fully adaptive to the traffic and network states. Through extensive experiments and results, we show that both the open-loop and closed-loop dynamic regulation techniques can significantly improve the network and system performance.

Abstract: Energy and temperature are the main constraints for modern high-performance multicore systems. To save power or increase performance, dynamic voltage and frequency scaling (DVFS) is widely applied in literally all computing systems. As CMOS technology continues scaling, FinFET has recently become the common choice for multicore systems. In contrast with planar CMOS, FinFET is characterized by lower delay under higher temperatures in super-threshold voltage region, an effect called temperature effect inversion (TEI). This paper explores TEI-aware performance improvement and energy savings for multicore systems. Our experimental results show that on average 15.70% throughput improvement or 31.26% energy savings can be achieved in steady state by a TEI-aware DVFS policy over a TEI-agnostic one. By further investigation, multiple sweet spots (SSs) resulting from TEI effects are observed. Based on these SS operation regimes, this paper introduces fast algorithms which provide iso-power maximum performance or iso-performance minimum energy consumption. Experimental results confirm the effectiveness of the proposed approach by exhibiting a $45.9 \times $ – $55.3 \times $ speedup when compared to state-of-the-art algorithms while losing only 0.22% or 0.68% in achieved performance or energy, respectively.

Abstract: Stencil computations are the basis to solve many problems related to Partial Differential Equations (PDEs). Obtaining the best performance with such numerical kernels is a major issue as many critical parameters (architectural features, compiler flags, memory policies, multithreading strategies) must be finely tuned. In this context, auto-tuning methods have been extensively used to improve the overall performance. However, the complexity of current architectures and the large number of optimizations to consider reduce the efficiency of this approach. This paper focuses on the use of Machine Learning to predict the performance of stencil kernels on multi-core architectures. Low-level hardware counters (e.g. cache-misses and TLB misses) on a limited number of executions are used to build our predictive model. We have considered two different kernels (7-point Jacobi and seismic wave modelling) to demonstrate the effectiveness of our approach. Our results show that performance can be predicted and that the best input configuration for stencil problems can be obtained by simulations of hardware counters and performance measurements.

Abstract: This paper proposes a model bank selection method for a large class of nonlinear systems with wide operating ranges. In particular, nonlinearity measure and H-gap metric are used to provide an effective algorithm to design a model bank for the system. Then, the proposed model bank is accompanied with model predictive controllers to design a high performance advanced process controller. The advantage of this method is the reduction of excessive switch between models and also decrement of the computational complexity in the controller bank that can lead to performance improvement of the control system. The effectiveness of the method is verified by simulations as well as experimental studies on a pH neutralization laboratory apparatus which confirms the efficiency of the proposed algorithm.

Abstract: Static analysis is an efficient approach for software assurance. It is indicated that its most effective usage is to perform analysis in an interactive way through the software development process, which has a high performance requirement. This paper concentrates on rule-based static analysis tools and proposes an optimized rule-checking algorithm. Our technique improves the performance of static analysis tools by filtering vulnerability rules in terms of characteristic objects before checking source files. Since a source file always contains vulnerabilities of a small part of rules rather than all, our approach may achieve better performance. To investigate our technique’s feasibility and effectiveness, we implemented it in an open source static analysis tool called PMD and used it to conduct experiments. Experimental results show that our approach can obtain an average performance promotion of 28.7% compared with the original PMD. While our approach is effective and precise in detecting vulnerabilities, there is no side effect.

Abstract: Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underuti-lization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.

Abstract: With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.

Abstract: Purpose From the theoretical perspectives of both multi-agent systems and smart business networks, empirical studies analyzing agent-based inter-organizational systems (ABIOS) in a real-life business setting are rare. The purpose of this paper is to investigate the impact of ABIOS on the performance of business networks. Design/methodology/approach This study presents a theoretical conceptual model portraying the influence of ABIOS on clients’ coordination structure and information architecture; and the impact of those structural alterations on business network performance in terms of the coordination, agility, and informational performances. To validate the model, a cross-case analysis was conducted in three logistics cases, namely, warehousing, freight forwarding, and intermodal transportation. Findings The application of ABIOS requires adjustments to the information architecture or the coordination structure, or both. Subsequently, those structural adjustments will stimulate improvements in the coordination, agility, and informational performances. Research limitations/implications The assessment of the clients’ performance improvement is done at the company level not at an aggregate network level. Moreover, the study only covers cases from the logistics sector. Practical implications This study explains the structural consequences of ABIOS applications. The adoption of an inter-organizational system is a strategic decision that requires support from multi-stakeholders. While the applications of ABIOS can offer performance improvement opportunities, adjustments must be made to the existing coordination structure or the information architecture, or both. Originality/value This study contributes to the smart business network literature and the ABIOS literature by presenting a validated conceptual model explaining the interplay among ABIOS, the coordination structure, informational structure, and business network performance, namely, the coordination, agility, and informational performances.

Abstract: In our previous paper, we examined the utility of LEDs for inter-satellite communication (ISC) in multiple small satellite networks and proposed an approach of the physical layer design that meets the requirements of the platform in terms of the critical physical layer design variables. These variables (or parameters) include the LED transmit power, photodetector active area, receiver bandwidth and link distance. One of the most important tasks for the visible light communication (VLC) system designer is how to ensure the required balance or trade-off among these variables in order to achieve the desired performance. In this work, we employed multi-objective optimization to determine physical layer design variables at which the signal-to-noise ratio (SNR) at the VLC receiver is maximized. We used the Non-dominated Sorting Genetic Algorithm II (NSGA-II) in MATLAB to determine the Pareto front of two conflicting objective functions, and then extracted the optimal solution using the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS). Analysis of the optimal solution showed that it yielded the maximum SNR within the set of non-dominated solutions at the Pareto front. We showed that using multi-objective optimization techniques for assignment of parameter values can yield more than 3 dB improvement in the SNR.

Abstract: In order to meet ever demanding requirements on powertrain efficiency and performance improvement, new concepts of automatic transmissions have been introduced recently, including electrified conve...

Abstract: In this paper, we propose a two-stage thermal-aware task scheduling policy which exploits the application and system architecture characteristics to decouple the mapping of task-graphs for the performance and peak temperature optimization into two stages. At the first stage, the algorithm collects the best mapping of task-graphs exploiting the application and architecture characteristics to minimize the makespan of the task-graphs. At the second stage, a light-weight online algorithm comprised of efficient thermal rank and combined power models is performed to map the task nodes to the real cores for temperature minimization while maintaining the best possible performance achieved in the first stage. Compared to the previous approaches which perform the performance and temperature optimization together, our method can reduce the online mapping algorithm complexity and improve its efficiency. Experiments on real benchmarks show that an average of 6.3°C peak temperature reduction and 6.8% performance improvement can be achieved compared to other existing methods.

Abstract: We present NICE, a key-value storage system design that leverages new software-defined network capabilities to build cluster-based network-efficient storage system. NICE presents novel techniques to co-design network routing and multicast with storage replication, consistency, and load balancing to achieve higher efficiency, performance, and scalability. We implement the NICEKV prototype. NICEKV follows the NICE approach in designing four essential network-centric storage mechanisms: request routing, replication, consistency, and load balancing. Our evaluation shows that the proposed approach brings significant performance gains compared to the current key-value systems design: up to 7× put/get performance improvement, up to 2× reduction in network load, 3× to 9× load reduction on the storage nodes, and the elimination of scalability bottlenecks present in current designs.

Abstract: Short term traffic flow prediction has become one of the important research fields in intelligent transportation system. The prediction of this traffic flow information quickly and accurately is important for traffic control and guidance to initiate the measuring steps well in advance. It makes the transport users better informed and makes the transport network smarter, safer and more coordinated. It plays a crucial role in individual dynamic route guidance, advance traffic information system (ATIS) and advance traffic management system (ATMS). This paper discusses the implementation of traffic flow prediction model using support vector machine. Rough set is used as a post processing tool to validate the prediction result. The objective is to improve traffic flow prediction performance. Data near Perungudi toll plaza in IT corridor in Chennai, India is used for the analysis. It is found that the use of rough set results in satisfactory performance improvement which is evaluated using mean square error as the performance measures. General Terms Intelligent Transportation Systems, Soft Computing Methods.

Abstract: Changes in Moore's law and Dennard's scaling made hardware accelerators critical for performance improvement, but configuring them for performance, area, and energy efficiency is hard and requires expert knowledge. High-Level Synthesis (HLS) tools enable hardware design for FPGAs to be done in high-level languages reducing the cost and time needed but still requiring configuration. This paper presents an open-source, flexible and virtualized autotuner for LegUp High-Level Synthesis parameters. Our optimization target was the Weighted Normalized Sum (WNS) of 8 hardware metrics. Weights were used to define 3 optimization scenarios targeting Area, Performance & Latency and Performance, plus a Balanced scenario. The autotuner found optimized HLS parameters that decreased WNS by up to 16% in the Balanced scenario, 23% in the Area scenario, 23% in the Performance scenario and 24% in the Performance & Latency scenario. This approach enables autotuning High-Level Synthesis parameters for different objectives by selecting weights for hardware metrics.

Abstract: Heterogeneous chip multicore processors (HCMPs) equipped with multiple voltage-frequency (V-F) operating points provide a wide spectrum of power-performance tradeoff opportunities. This work targets the performance of HCMPs under a power cap. We show that for any performance optimization technique to work under power constraints, the default set of V-F operating points in HCMPs must be first filtered based on the application’s power and performance characteristics. Attempting to find operating points of maximum performance by naively walking the default set of operating points leads the application to inefficient operating points which drain power without significant performance benefit. We call these points Power Holes (PH) . Contrary to intuition, we show that even using a power-performance curve of Pareto-optimal operating points still degrades performance significantly for the same reason. We propose PH-Sifter, a fast and scalable technique that sifts the default set of operating points and eliminates power holes. We show significant performance improvement of PH-Sifter compared to Pareto sifting for three use cases: (i) maximizing performance for a single application, (ii) maximizing system throughput for multi-programmed workloads, and (iii) maximizing performance of a system in which a fraction of the power budget is reserved for a high-priority application. Our results show performance improvements of 13, 27, and 28 percent on average that reach up to 52, 91 percent, and 2.3 $\times$ , respectively, for the three use cases.

Abstract: The limitations and rigidness of current use of spectrum resources have fostered the design of new power multiplexing techniques to improve frequency efficiency and flexibility. These techniques are based on the simultaneous transmission of different services on the same channel with different power distribution. At the receiver side Log-likelihood ratio (LLR) probability density functions have been so far optimized for single layer systems, so the reception quality of multilayer signals with the existing LLR algorithms is degraded. This paper proposes a new LLR probability density function, including corrections for the multilayer influence, in order to improve reception performance. Simulation results are also included to test the performance improvement in terms of the receiving SNR threshold.

Abstract: We analyze performance of a class of time-delay first-order consensus networks from a graph topological perspective and present methods to improve it. The performance is measured by the network's square of ℋ 2 -norm and it is shown that it is a convex function of Laplacian eigenvalues and the coupling weights of the underlying graph of the network. First, we propose a tight convex, but simple, approximation of the performance measure in order to achieve lower complexity in our design problems by eliminating the need for eigen-decomposition. Next, we present three methods to improve the performance by growing, re-weighting, or sparsifying the underlying graph of the network. It is shown that our proposed algorithms provide near-optimal solutions with lower complexity with respect to existing methods in literature.