PCI-X

Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

Abstract: Communication from a processor in a computer system to a remote input/output (I/O) unit in an expansion drawer using a Peripheral Component Interface (PCI) protocol is optimized to improve system performance. An InfiniBand (IB) protocol link is used to couple the I/O unit to the computer system. In one case the computer system uses a PCI to IB bridge to couple from the processor to a corresponding IB to PCI bridge in the expansion drawer which couples to the I/O unit using a PCI link. Intelligence is added to the PCI to IB bridge to optimize communication by assigning selected PCI command sequences to optimized Macro IB commands. The IB to PCI link has like intelligence to receive and convert the Macro IB commands to the corresponding selected PCI command sequences. Optimization is accomplished by either a learning routine or by a logic state machine that generate the optimized Macro commands. In other embodiments, a modified operating system (OS) or software running on an unmodified OS intercepts PCI commands and generate the Macro IB commands which are sent to the IB to PCI bridge via a host communication adapter (HCA). In other embodiments, device drivers are linked to a library of software routines which intercept the PCI commands. In this case, the library generates the optimized Macro IB commands.

Abstract: A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector The PCB can be configured at fabrication time to enable a variety of configurations for operation Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB