Packet-switching node

Abstract: A packet switching node (20) which processes data packets containing routing tag signals indicative of the output port destination thereof and which routes these data packets to the specified output ports. A plurality of queue selectors (22) are individually coupled between a plurality of input ports (21) and a plurality of queue sets (23) that comprise a plurality of queues which store and forward data packets applied thereto as a function of output port destination. Each of the plurality of queue selectors (22) sort the data packets applied thereto in accordance with the output port destination thereof. The queues of each queue sets (23) are coupled to different output arbitrators (24) which control routing to a particular output port (25). The packet switching node (20) eliminates the problem of contention between data packets arriving at an input port of the node whose destinations are different output ports. The packet switching node sorts applied data packets according to output port destination to reduce contention and hence has improved performance and higher throughput. The present invention also contemplates a method of processing applied data packets containing routing tag signals indicative of the output port destinations to which the data packets are to be applied. The method comprises sorting and storing the data packets in accordance with the routing tag signals, arbitrating among data packets that have been stored that contend for the same output port, and then routing the selected data packet to the output port identified in the routing tag signal.

Abstract: A load balancing circuit arrangement for use with a packet switching node. The packet switching node processes applied data packets containing routing tag signals indicative of the output port destinations to which the data packets are addressed, and routes these packets to the identified output ports. The present invention a load balancing circuit coupled to the packet switching node which monitors the output port addresses of the applied data packets and monitors the number of data packets addressed to each of the output ports. The load balancing circuit is adapted to generate new routing tag signals identifying output port addresses which redistribute the output port load. The load balancing circuit arrangement includes a tag selection circuit coupled to the load balancing circuit and the packet switching node which selectively replaces the routing tag signals of the applied data packets with the new routing tag signals in order to redistribute and balance the output port load. The load balancing circuit comprises a minimum index circuit for generating the new routing tag signals and an adder circuit coupled thereto. The minimum index circuit combines the new routing tag signals with offset signals that modify the new routing tag signals in order to implement a predetermined output port priority scheme. The load balancing circuit arrangement may be employed in both multiple queue and multiport memory packet switching nodes employed in computer or telephone communications applications.

Abstract: A method of transmitting high speed (1 Gbits/sec), packetized, integrated voice/data through a communications network. This invention, more specifically, deals with the word by word transmission of packets on a parallel transmission bus.

Abstract: The use of optical processing to perform switch routing functions permits real-time routing of packets at high speed. The architecture of a 2*2 photonic packet switching node using optically processed fixed-directory routing, contention resolution using deflection routing, and synchronization is presented. Simplified optically processed self-routing procedures are found for banyan and lattice networks. Although lattice networks require a larger number of switching elements than banyan networks, they have a simpler interconnection field, and unlike banyan networks, the self-routing rule for lattices can avoid any internal blocking. The layout of a self-routing 2-D lattice, using 2*2 switches and a smart pixel, is described. Based on a first-arrival self-routing rule, an additional processing logic is required to perform routing. >