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  4. 1996
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  3. Orthogonal array testing
  4. 1996
Showing papers on "Orthogonal array testing published in 1996"
Journal Article•10.1016/0950-5849(96)01103-2•
Proportional sampling strategy: guidelines for software testing practitioners☆

[...]

Felix T.S. Chan1, Tsong Yueh Chen2, I. K. Mak2, Yuen Tak Yu2•
University of Hong Kong1, University of Melbourne2
01 Jan 1996-Information & Software Technology
TL;DR: In this paper, it is discussed how the proportional sampling strategy can be applied effectively in practice and some practical issues that need to be attended are identified and guidelines to deal with these issues are suggested.
Abstract: Recently, several sufficient conditions have been developed that guarantee partition testing to have a higher probability of detecting at least one failure than random testing One of these conditions is that the number of test cases selected from each partition is proportional to the size of the partition We call such a method of allocating test cases the proportional sampling strategy Although this condition is not the most general one, it is the most easily and practically applicable one In this paper, we discuss how the proportional sampling strategy can be applied effectively in practice Some practical issues that need to be attended are identified and guidelines to deal with these issues are suggested

161 citations

Journal Article•10.1109/24.556577•
Needed resources for software module test, using the hyper-geometric software reliability growth model

[...]

Rong-Huei Hou1, Sy-Yen Kuo1, Yi-Ping Chang2•
National Taiwan University1, Soochow University (Taiwan)2
01 Dec 1996-IEEE Transactions on Reliability
TL;DR: Experimental results show that the OPT/RA method can improve the quality and reliability of the software system much more than the simple allocation methods.
Abstract: Considerable testing resources are required during software module testing. This paper, based on the 'hyper-geometric distribution software reliability growth model' (HGDM) investigates two optimal resource allocation (OPT/RA) problems in software module testing: (1) minimization of the number of software faults (NSF) still undetected in the system after testing, given a fixed amount of testing resources; and (2) minimization of the total amount of testing resources required, given the NSF still undetected in the system after testing. Based on the concepts of average allocation and proportional allocation, two simple allocation methods are introduced. Experimental results show that the OPT/RA method can improve the quality and reliability of the software system much more than the simple allocation methods. Therefore, the OPT/RA method is very efficient for solving the 'testing resource allocation' problem.

45 citations

Proceedings Article•10.5555/227726.227845•
A demand-driven analyzer for data flow testing at the integration level

[...]

Evelyn Duesterwald1, Rajiv Gupta1, Mary Lou Soffa1•
University of Pittsburgh1
1 May 1996
TL;DR: A demand-driven analyzer is developed and implemented and experimentally compared its performance during integration testing with the performance of a traditional exhaustive analyzer, and an incremental analyzer.
Abstract: Data-flow testing relies on static analysis for computing the definition-use pairs that serve as the test case requirements for a program. When testing large programs, the individual procedures are first tested in isolation during unit testing. Integration testing is performed to specifically test the procedure interfaces. The procedures in a program are integrated and tested in several steps. Since each integration step requires data-flow analysis to determine the new test requirements, the accumulated cost of repeatedly analyzing a program can contribute considerably to the overhead of testing. Data-flow analysis is typically computed using an exhaustive approach or by using incremental data-flow updates. This paper presents a new and more efficient approach to data-flow integration testing that is based on demand-driven analysis. We developed and implemented a demand-driven analyzer and experimentally compared its performance during integration testing with the performance of (i) a traditional exhaustive analyzer, and (ii) an incremental analyzer. Our experiments show that demand-driven analysis is faster than exhaustive analysis by up to a factor of 25. The demand-driven analyzer also outperforms the incremental analyzer in 80% of the test programs by up to a factor of 5.

33 citations

Proceedings Article•10.5555/227726.227838•
A reliability model combining representative and directed testing

[...]

Brian Mitchell1, Steven J. Zeil1•
Old Dominion University1
1 May 1996
TL;DR: A model is presented which permits representative and directed testing to be used in conjunction, using order statistics to combine the observed failure rates of faults no matter how those faults were detected.
Abstract: Directed testing methods, such as functional or structural testing, have been criticized for a lack of quantifiable results. Representative testing permits reliability modeling, which provides the desired quantification. Over time, however, representative testing becomes inherently less effective as a means of improving the actual quality of the software under test. A model is presented which permits representative and directed testing to be used in conjunction. Representative testing can be used early, when the rate of fault revelation is high. Later results from directed testing can be used to update the reliability estimates conventionally associated with representative methods. The key to this combination is shifting the observed random variable from interfailure time to a post-mortem analysis of the debugged faults, using order statistics to combine the observed failure rates of faults no matter how those faults were detected.

17 citations

Proceedings Article•10.1109/APSEC.1996.566745•
A class testing technique based on data bindings

[...]

Heechern Kim1, Chisu Wu•
Seoul National University1
4 Dec 1996
TL;DR: The authors present a testing technique based on data bindings for testing a class that considers the correctness of a class with regard to data interactions of its member functions and is based on an adaptation of flow graph-based techniques for testing object-oriented classes.
Abstract: The authors present a testing technique based on data bindings for testing a class. Data bindings can be used to measure the interface between the modules of a system and reflect the possibility of data interactions between modules. Their approach considers the correctness of a class with regard to data interactions of its member functions and is based on an adaptation of flow graph-based techniques for testing object-oriented classes. A class is fragmented into smaller pieces, called a slice-flow graph associated with each data member. Class testing approaches typically invoke sequences of methods in varying orders. Their approach can generate test cases by applying a flow graph-based class testing technique to each slice-flow graph. It is useful for determining which sequences of methods should be tested. Before applying a flow graph-based testing technique, they apply state-testing only to simple MM-paths which represents actual data bindings. The result is reflected in the next step to reduce efforts for generating test cases.

10 citations

Patent•
Method of utilizing redundancy testing to substitute for main array programming and AC speed reads

[...]

Edward Hsia1, Darlene Hamilton1, Jose H. Hernandez1•
Advanced Micro Devices1
24 May 1996
TL;DR: In this article, a method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cell only.
Abstract: A method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cells only. There is a major savings of testing time with no decrease in quality of the final product.

7 citations

Proceedings Article•10.1109/GLSV.1996.497621•
Test generation for networks of interacting FSMs using symbolic techniques

[...]

Fabrizio Ferrandi1, Franco Fummi1, Enrico Macii, Massimo Poncino, Donatella Sciuto •
Polytechnic University of Milan1
22 Mar 1996
TL;DR: A new testing strategy for networks of interacting FSMs is presented, which allows us to generate test patterns for faults in the network by separately handling the network's components.
Abstract: This paper presents a new testing strategy for networks of interacting FSMs. The approach allows us to generate test patterns for faults in the network by separately handling the network's components. The proposed algorithms are fully symbolic; therefore, they allow the manipulation of large designs. Experimental results, though preliminary, are promising.

7 citations

Proceedings Article•10.5555/227726.227844•
An exact array reference analysis for data flow testing

[...]

István Forgács1•
Hungarian Academy of Sciences1
1 May 1996
TL;DR: In this article, the authors present an algorithm that precisely determines the definition-use pairs for arrays within a large domain and avoid negation in formulae, which seems to be the biggest problem in all previous methods.
Abstract: Data-flow testing is a well-known technique, and it has proved to be better than the commercially-used branch testing. The problem with data-flow testing is that, apart from scalar variables, only approximate information is available. This paper presents an algorithm that precisely determines the definition-use pairs for arrays within a large domain. There are numerous methods addressing the array data-flow problem; however, these methods are only used in the optimization or parallelization of programs. Data-flow testing, however, requires at least one real solution of the problem for which the necessary program path is executed. Contrary to former precise methods, we avoid negation in formulae, which seems to be the biggest problem in all previous methods.

6 citations

Proceedings Article•10.1109/CCECE.1996.548063•
Automated behavioral testing of VHDL components

[...]

P. Walsh, Daniel Hoffman
26 May 1996
TL;DR: VHDLGEN is a prototype method and tool for algorithmic testing of VHDL designs, adapted from a successful approach to testing software components, and is oriented towards highly automated testing, where the driver generates the inputs, runs the tests, and checks the outputs for correctness.
Abstract: Design reuse is essential for dealing with complex integrated circuits and printed circuit boards. The use of a hardware description language such as VHDL is becoming a requirement for this kind of reuse. The current practice is to model the design component in VHDL and to test the design's behavior using a testbench, which applies test cases and reports deviations of actual behavior from expected behavior. In this paper we present VHDLGEN, a prototype method and tool for algorithmic testing of VHDL designs, adapted from a successful approach to testing software components. Testing with VHDLGEN involves a special interface to the component under test, a scripting language, and a driver generator. VHDLGEN is oriented towards highly automated testing, where the driver generates the inputs, runs the tests, and checks the outputs for correctness. We present evidence that the VHDLGEN approach is feasible. Our experience with algorithmic testing of software components suggests that VHDLGEN will scale up to more complex designs and will be adaptable to designs in object-oriented HDLs as they become available.

5 citations

Proceedings Article•10.1109/ATS.1996.555137•
Testing and diagnosis of board interconnects in microprocessor-based systems

[...]

Po-Ching Hsu, Sying-Jyan Wang
20 Nov 1996
TL;DR: A low-cost board-level testing method for printed circuit boards in microprocessor-based systems by replacing the CPU with a bus emulator to test faults on wiring interconnects to reach the controllability and observability offered by in-circuit testing.
Abstract: In this paper we propose a low-cost board-level testing method for printed circuit boards in microprocessor-based systems. The fault detection is achieved by replacing the CPU with a bus emulator to test faults on wiring interconnects. Test patterns are sent by the bus emulator and the results are collected by it later for analysis. We also discuss how to derive minimum test sets for the diagnosis of all modeled faults. Multiple-board systems can be tested by hierarchically applying our method. With this approach, board testing is conducted in a way similar to functional testing while at the same time reach the controllability and observability offered by in-circuit testing.

2 citations

Proceedings Article•10.1109/ASWEC.1996.534133•
More on the E-measure of subdomain testing strategies

[...]

Tsong Yueh Chen1, Yuen Tak Yu1•
University of Melbourne1
14 Jul 1996
TL;DR: New sufficient conditions for subdomain testing to be better than random testing are deduced, simpler and more easily applicable than many of those previously found.
Abstract: The expected number of failures detected (the E-measure) has been found to be a useful measure of the effectiveness of testing strategies. This paper takes a fresh perspective on the formulation of the E-measure. From this, we deduce new sufficient conditions for subdomain testing to be better than random testing. These conditions are simpler and more easily applicable than many of those previously found. Moreover, we obtain new characterisations of subdomain testing strategies in terms of the E-measure.
Proceedings Article•10.1109/CMPSAC.1996.544612•
Applying conventional testing techniques for class testing

[...]

In-S Chung1, Malcolm Munro, W.K. Lee, Y.R. Kwon•
Hallym University1
19 Aug 1996
TL;DR: The technique is a mixture of code-based and specification-based testing techniques in the sense that it uses information derived from codes using symbolic execution together with information from specifications using FSMs for testing activities.
Abstract: We discuss how conventional testing criteria such as branch coverage can be applied to the testing of member functions inside a class. To support such testing techniques we employ symbolic execution techniques and finite state machines (FSMs). Symbolic execution is performed on the code of a member function to identify states that are required to fulfil a given criterion. We use FSMs to generate a sequence of member functions leading to the identified states. Our technique is a mixture of code-based and specification-based testing techniques in the sense that it uses information derived from codes using symbolic execution together with information from specifications using FSMs for testing activities.
Journal Article•10.1109/32.553698•
A framework for specification-based testing

[...]

P. Stocks1, David Carrington2•
Rutgers University1, University of Queensland2
01 Nov 1996-IEEE Transactions on Software Engineering
TL;DR: A test template framework is introduced as useful concepts in specification-based testing and formally defines test data sets and their relation to the operations in a specification and to other test data set, providing structure to the testing process.
Abstract: Test templates and a test template framework are introduced as useful concepts in specification-based testing. The framework can be defined using any model-based specification notation and used to derive tests from model-based specifications-in this paper, it is demonstrated using the Z notation. The framework formally defines test data sets and their relation to the operations in a specification and to other test data sets, providing structure to the testing process. Flexibility is preserved, so that many testing strategies can be used. Important application areas of the framework are discussed, including refinement of test data, regression testing, and test oracles.

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