TL;DR: In this paper, a rounding circuit is provided that includes an input for receiving a 2's complement number to be rounded, where S represents a sign bit, X represents one or more bits to round and keep, and Y represents a bit to be discarded.
Abstract: A rounding circuit is provided that includes an input for receiving a 2's complement number to be rounded. The 2's complement number has a format SXY, where S represents a sign bit, X represents one or more bits to round and keep, and Y represents one or more bits to be discarded. The rounding circuit also includes first logic for adding a rounding bias to the 2's complement number, and second logic for at least one of subtracting the sign bit S from the 2's complement number, or adding the inverted sign bit !S to the 2's complement number. Moreover, the rounding circuit includes third logic for truncating Y bits from a result produced by the first and second logic to produce a rounded 2's complement number having a format SX.
TL;DR: In this article, the authors disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric, which can be achieved using an exclusive OR function with the preselected bits of the binary representation and the hard decision bit to form the soft symbol.
Abstract: There is disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric. When a hard decision bit is a zero, a preselected number of bits of a binary representation of the branch metric are concatenated with a hard decision bit to form the soft symbol. When the hard decision bit is a one, the ones complement of the preselected number of bits of the binary representation of the branch metric are concatenated with the hard decision bit to form the soft symbol. The concatenation function can be achieved using an exclusive OR function with the preselected bits of the binary representation of the branch metric and the hard decision bit to form the soft symbol. The hard decision bit may be selectable from more than one source.
TL;DR: In this paper, a decoding system and method for a radiotelephone system carrying digital messages is described. But the decoding scheme is based on normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence.
Abstract: A decoding system and method is disclosed for a radiotelephone system carrying digital messages. A set of multibit high auto-correlation, low cross-correlation synchronization words and their ones complement inverses are employed for message synchronization and supervisory functions. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is substituted. This selected sequence of binary levels is decoded and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated. If the Hamming distance calculated yields a number less than or equal to a number equal to the synchronization error correction capability of the coding function, the decoded sequence is accepted as correct. If the Hamming distance calculation yields a number greater than the error correction capability value, a new set of substituted binary levels is tried.
TL;DR: In this paper, a radiotelephone system in which the signalling protocol for the system is embedded in the frame synchronization of the digital messages transmitted on the system was described. But the decoding procedure was not described.
Abstract: A radiotelephone system in which the signalling protocol for the system is embedded in the frame synchronization of the digital messages transmitted on the system. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is subtituted (3003). This selected sequence of binary levels is decoded (3101) and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated (3207). If the Hamming distance calculation yields a number greater than the error correction capability of thge coding function, a new set of substituted binary levels is tried (3205), otherwise the decoded sequence is accepted as correct.
TL;DR: In this paper, the two-to-one complementing circuitry for N-bit binary numbers is described and the carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage.
Abstract: Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.