OMAP

Abstract: Due to the ever increasing constraints on power consumption in embedded systems, this paper addresses the need for an efficient power modeling and estimation methodology based tool at system-level On the one hand, today's embedded industries focus more on manufacturing RISC processor-based platforms as they are cost and power effective On the other hand, modern embedded applications are becoming more and more sophisticated and resource demanding: multimedia (H264 encoder and decoder), software defined radio, GPS, mobile applications, etc The main objective of this paper focuses on the scarcity of a fast power modeling and an accurate power estimation tool at the system-level for complex embedded systems In this paper, we propose a standalone simulation tool for power estimation at system-level As a first step, we develop the power models at the functional level This is done by characterizing the power behavior of RISC processor based platforms across a wide spectrum of application benchmark to understand their power profile Then, we propose power models to cost-effectively estimate its power at run-time of complex embedded applications The proposed power models rely on a few parameters which are based on functional blocks of the processor architecture As a second step, we propose a power estimation simulator which is based on cycle-accurate full system simulation framework The combination of the above two steps provides a standalone power estimation tool at the system-levelThe effectiveness of our proposed methodology is validated through an ARM9, an ARM Cortex-A8 and an ARM Cortex-A9 processor designed around the OMAP5912, OMAP 3530 and OMAP4430 boards respectively The efficiency and the accuracy of our proposed tool is evaluated by using a variety of basic programs to complex benchmarks Estimated power values are compared to real board measurements for the different processor architecture based platforms Our obtained power estimation results provide less than 3% of error for ARM940T processor, 29% for ARM Cortex-A8 processor and 42% for ARM Cortex-A9 processor based platforms when compared to the other state-of-the-art power estimation tools

Abstract: Platform-based design of SoC, as practiced by Texas Instruments, has two key characteristics: platforms are defined hierarchically and software plays as critical a role as hardware We illustrate these points using the TI OMAP™ platform as an example Development of new platform family members requires a number of system-level design processes to be carried out Multiprocessor platforms need a particular focus on SW architectures We conclude with a detailed description of the TI Wireless SoC platform

Abstract: Full HD video coding has become an essential requirement for consumer mobile applications. The functionality ranges from single channel encoding (camcorder) and decoding (video playback), to more complex use cases such as video conferencing (encode + decode) and transcoding. There is increasing demand for higher visual quality, and the wide spectrum of video content requires support for multiple standards. Low power and area efficiency are also equally critical requirements for these applications. Low power video codecs [1–3] employ hardwired implementations targeted to a specific standard and address either encode or decode. Low power is typically achieved by using single codec optimized circuitry and massive parallelism so that the design can run at lower voltage and frequency. Such an approach is not area efficient for an application processor which needs to support multiple (10+) video standards and a range of rate-distortion flexible encoding algorithms. Multicore programmable processors [5] can support multiple standards, but are not scalable to meet full HD performance of complex standards like H.264 High Profile (HP) in a low-power CMOS process, and are inefficient in terms of area and power. The approach [4] of decoupling stream processing and pixel processing, and using a 2 mac-roblock pipeline helps meet the performance, but introduces a frame delay resulting in higher latency. Video conferencing not only requires low latency but also requires encoding with a fixed limit on the number of bits per slice [RFC3984: RTP Payload Format for H.264 Video]. The 2 macroblock pipeline cannot support this requirement without impacting the performance or the bitrate. The TI OMAP 4 application processor addresses these challenges with a dedicated video coding engine built with algorithm-specific hardware accelerators.

Abstract: A smart meter is one of the key elements of smart girds. An attacker can compromise smart meters by injecting malicious codes, and take financial benefits by modifying memory contents of the smart meters. An attestation scheme can prevent such a memory forgery attack as verifying memory contents. In smart grids, however, attestation processes are remotely performed through networks by a faraway utility. Therefore, attestation processes are exposed to network attacks such as man-in-the-middle (MITM) attacks. Even though existing attestation mechanisms detect local attacks such as the memory forgery, they are vulnerable to network attacks since they adopt a two-way attestation so-called a challenge-response protocol. In this paper, we propose a novel attestation mechanism, termed One-way Memory Attestation Protocol(OMAP), not only to detect local attacks, but also to defend against network attacks. Instead of using the two-way attestation, OMAP adopts an one-way attestation protocol, OMAP conducts a pre-defined internal algorithm, generates a checksum, and sends it to a verifier in one direction. Thus, OMAP does not require any information (e.g., challenges) from a verifier that can be exploitable by an adversary. In our experiments, as a smart meter scans only 0.004% of its memory, OMAP enables a verifier to detect memory modification with 95% probability if an attacker changes 20% of the memory.