nvSRAM

Abstract: The current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors Discussed next are recent developments in the field Pb(Zr X ,Ti 1 - X )O 3 (PZT) and SrBi 2 Ta 2 O 9 (SBT) films are being used to produce 013 μm and 018 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits A new class of FeRAM called 6T4C-containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)-has been commercially produced This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies

Abstract: Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

Abstract: This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

Abstract: A semiconductor device which can be re-used even if the read protection is set for a non-volatile memory included therein, and electronic equipment including such a semiconductor device. The data written in a memory cell array is protected from being read out from the outside for security. Only when erase of all data in the memory cell array is detected, the read protection is released. Thus, a microcomputer can be refused. The detection with respect to whether or not all data has been erased can be accomplished through execution of a flash erase operation or by reading out all address data. A read protection control circuit includes an EEPROM for storing information that the read protection is enabled. A plurality of such EEPROM's are used. If the read protection for the memory cell array is enabled, the erase/write to the EEPROM's are inhibited. The memory cell array is controlled separately from the EEPROM's. In the normal operation mode, the read-out of data by CPU is permitted. Such a configuration may be applied to a semiconductor device including a gate array block.