Nuclear electronics

Abstract: The readout electronics designed for the DO Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the DO Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16-bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed.

Abstract: Three simple charge division circuits were assembled and tested as 2-D position encoding readouts for multi-channel photomultiplier tubes (MC-PMT). They were evaluated with an 8/spl times/8 array of individual scintillators (2/spl times/2/spl times/10 mm BGO) coupled to a 64 channel MC-PMT (Philips XP1722) via 25 cm long, 2 mm diameter, double clad, optical fibers (Kuraray). This type of gamma-ray imaging detector has many potential applications in medical and industrial imaging. Though independent channel readout would allow for the discrimination of scatter within the array, and higher count rates, it would also require an excessive amount of supporting electronics. This is especially true for systems comprised of many MC-PMTs. In this study, the number of channels being read out was reduced from 64 to 4 using three different simple resistor networks. These circuits take advantage of the discretized nature of the scintillator array, the low interchannel crosstalk of the MC-PMT and low input impedance current-sensitive preamplifiers. For each circuit, the scintillator identification accuracy was compared. The identification accuracy as a function of deposited energy was also determined by exposure to various gamma-ray emitters. It was found that the preamplifier circuit noise contributed the most to the degradation of the detector's spatial response so several low noise op amps were evaluated. It was also determined that keeping the preamplifier input impedance small was necessary for accurate positioning. The coincidence timing resolution of the detector (15 ns) is only slightly degraded by the readout circuit.

Abstract: A low-noise, mixed-signal, 128-channel CMOS integrated circuit containing the complete readout electronics for the BABAR Silicon Vertex Tracker has been developed. The outstanding feature of the present implementation is the ability to perform simultaneously low-level signal acquisition, derandomizing data storage, sparsification and data transmission on a single monolithic chip. The signals from the detector strips are amplified, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time of 100 ns, 200 ns, 300 ns, or 400 ns, and then presented to a time-over-threshold processor to implement a compression type analog-to-digital conversion. The digital information is stored, sparsified and read out through a serial link upon receipt of a command. The digital section operates from a 60 MHz incoming clock. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 k transistors. The first full-scale prototype was fabricated in a radiation soft 0.8 /spl mu/m, 3-metal CMOS process. The same circuit is now being fabricated in an analogous radiation hard technology.

Abstract: A monolithic active pixel sensor (MAPS) for charged particle tracking based on a novel detector structure was proposed, simulated, fabricated and tested. The detector designed accordingly to this idea is inseparable from the readout electronics, since both of them are integrated onto the same, standard for a CMOS process, low-resistivity silicon wafer. The individual pixel is comprised of only 3 MOS transistors and a photodiode collecting the charge created in a thin undepleted epitaxial layer. This approach provides the whole detector surface sensitive to radiation (100% fill factor) with reduced pixel pitch(very high spatial resolution). This yields a low cost, high resolution and thin detecting device. The detailed device simulations using an ISE-TCAD package have been carried out in order to study a charge collection mechanism and to validate the proposed idea. Consequently, two prototype chips have been fabricated using 0.6 /spl mu/m and 0.35 /spl mu/m CMOS processes. Special radiation tolerant layout techniques were used in the second chip design. Both chips were tested and fully characterised. The pixel conversion gain was calibrated using 5.9 keV photons and prototype devices were exposed to the 120 GeV/c pion beams at CERN. Obtained results preceded by general design ideas and simulation results are reviewed.