Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

Abstract: Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Abstract: We report on the most aggressively scaled ferroelectric field effect transistor so far. These were successfully fabricated using ferroelectric Si:HfO 2 in a 28 nm HKMG stack (TiN/Si:HfO 2 /SiO 2 /Si). For a ± 5 V program/erase operation with pulses as short as 20 ns, reliable threshold voltage shifts were observed resulting in a memory window of about 0.9 V. We further demonstrate endurance characteristics matching demands of current nonvolatile memories utilizing wear leveling. Low retention loss was observed and extrapolated 10-year data storage can be expected.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.

Abstract: Nonvolatile processors offer a number of desirable properties including instant on/off, zero standby power and resilience to power failures. This paper presents a fabricated nonvolatile processor based on ferroelectric flip-flops. These flipflops are used in a distributed fashion and are able to maintain system states without any power supply indefinitely. An efficient controller is employed to achieve parallel reads and writes to the flip-flops. A reconfigurable voltage detection system is designed for automatic system backup during power failures. Measurement results show that this nonvolatile processor can operate continuously even under power failures occurring at 20 KHz. It can backup system states within 7μs and restore them within 3 μs. Such capabilities will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.

Abstract: B- and N-doped carbon nanotubes (CNTs) with controlled workfunctions were successfully employed as charge trap materials for solution processable, mechanically flexible, multilevel switching resistive memory. B- and N-doping systematically controlled the charge trap level and dispersibility of CNTs in polystyrene matrix. Consequently, doped CNT device demonstrated greatly enhanced nonvolatile memory performance (ON-OFF ratio >10(2), endurance cycle >10(2), retention time >10(5)) compared to undoped CNT device. More significantly, the device employing both B- and N-doped CNTs with different charge trap levels exhibited multilevel resistive switching with a discrete and stable intermediate state. Charge trapping materials with different energy levels offer a novel design scheme for solution processable multilevel memory.

Abstract: We report the fabrication of completely CMOS-compatible ferroelectric field-effect transistors (FETs) by stabilization of a ferroelectric phase in 10-nm-thin Si:HfO2. The program and erase operation of this metal-ferroelectric-insulator-silicon FET (MFIS) with poly-Si/TiN/Si:HfO2/SiO2/Si gate stack is compared to the transient switching behavior of a TiN-based metal-ferroelectric-metal (MFM) capacitor. Polarization reversal in the MFM capacitor follows a characteristic time and field dependence for ferroelectric domain switching, leading to a higher switching speed with increasing applied field. Similar observations were made for the material when implemented into an MFIS structure. Nonvolatile switching was observed down to 20-ns pulsewidth, yielding a memory window (MW) of 1.2 V. Further increase in gate bias or pulsewidth led to charge injection and degradation of the MW. Retention measurements for up to 106 s suggest a retention of more than ten years.

Abstract: A flexible field-effect transistor with a poly(3-hexylthiophene) (P3HT) active channel and a ferroelectric poly(vinlyidene fluoride-co-trifluoro ethylene) (PVDF-TrFE) insulator exhibits gate-voltage-controllable multilevel non-volatile memory characteristics with highly reliable data retention and endurance.

Abstract: Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Abstract: A method for protecting a password of a computer having a non-volatile memory is disclosed. A password is stored in a non-volatile memory of a computer. The computer is then transitioned to a power saving state. In response to a detection of an unauthorized access to the non-volatile memory during the power saving state transition, a password input is requested from a user. The computer returns to a power-on state from the power saving state when there is a success in authentication of the input password.

Abstract: We demonstrate that unmodified commercial Flash memory can provide two important security functions: true random number generation and digital fingerprinting. Taking advantage of random telegraph noise (a type of quantum noise source in highly scaled Flash memory cells) enables high quality true random number generation at a rate up to 10Kbits / second. A scheme based on partial programming exploits process variation in threshold voltages to allow quick generation of many unique fingerprints that can be used for identification and authentication. Both schemes require no change to Flash chips or interfaces, and do not require additional hardware.

Abstract: Intensive investigations have been launched worldwide on the resistive switching (RS) phenomena in transition metal oxides due to both fascinating science and potential applications in next generation nonvolatile resistive random access memory (RRAM) devices. It is noteworthy that most of these oxides are strongly correlated electron systems, and their electronic properties are critically affected by the electron-electron interactions. Here, using NiO as an example, we show that rationally adjusting the stoichiometry and the associated defect characteristics enables controlled room temperature conversions between two distinct RS modes, i.e., nonvolatile memory switching and volatile threshold switching, within a single device. Moreover, from first-principles calculations and x-ray absorption spectroscopy studies, we found that the strong electron correlations and the exchange interactions between Ni and O orbitals play deterministic roles in the RS operations.

Abstract: New donor–acceptor conjugated copolymer, PSeDPP, consisting of selenophene (Se) and 3,6-dithiophen-2-yl-2,5-dialkylpyrrolo[3,4-c]pyrrole-1,4-dione (DPP), was developed for high performance ambipolar field-effect transistors (FETs) and nonvolatile memory applications. The maximum absorption peak and optical band gap of PSeDPP thin film were observed at 849 nm and 1.29 eV, respectively, indicating the strong intramolecular and intermolecular charge transfer. The polymer crystallinity and FET mobility was significantly enhanced as increasing the solvent boiling point and thermal treatment based on the results from four processing solvents of chloroform, chlorobenzene, o-dichlorobenzene and 1,2,4-trichlorobenzene, as evidenced by TEM, XRD, and AFM. The PSeDPP-based FET processed from1,2,4-trichlorobenzene exhibited a dense nanofiber morphology with lamellar chain packing, leading to the relatively high hole and electron mobility up to 1.62 and 0.14 cm2 V−1 s−1, respectively. PSeDPP was also found to exhibit the first transistor memory characteristics for ambipolar conjugated polymers. The retention time of the FET-based nonvolatile memory devices could maintain the high- and low-conductance states longer than 104 s, and the on-off current ratios of 103–104 at the read voltage of 0 V. These results revealed that PSeDPP had potential applications for flexible electronic device applications.

Abstract: In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area.

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Abstract: A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM.

Abstract: Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous increasing of tunnel magneto-resistance(TMR) ratio of the MTJ inspires the development of multi-level cell (MLC) STT-RAM, which allows multiple data bits be stored in a single memory cell. Two types of MLC STT-RAM cells, namely, parallel MLC and series MLC, were also proposed. The storage margin of a MLC STT-RAM cell, i.e., the distinction between the lowest and highest resistance states, is partitioned into multiple segments for multi-level data representation. As a result, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations and the thermal-induced randomness of MTJ switching. In this work, we systematically analyze the variation sources of MLC STT-RAM designs and their impacts on the reliability of the read and write operations. On top of that, we also discuss the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the MLC STT-RAM cells from statistical design perspective. Our simulation results show that under the current available technology, series MLC STT-RAM demonstrates overwhelming benefits in the read and write reliability compared to parallel MLC STT-RAM and could potentially satisfy the requirement of commercial practices.

Abstract: A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.

Abstract: We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor (CG) and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time (tre >; 5s).

Abstract: Figure 1–1 shows an access-speed vs. density map of existing memories. The ideal memory, a fast and dense non-volatile memory with unlimited endurance, does not exist. Consequently, most systems use a combination of working memories such as SRAM and DRAM and storage memories such as NAND Flash and HDD as shown in Fig. 1–2.

Abstract: Solution-processed mechanically flexible resistive random access memories are fabricated using Ag(2)Se nanoparticles; the fabricated Ag/Ag(2)Se/Au memory devices on flexible poly-ethylene-naphthalate substrates show bipolar switching memory characteristics, with low voltage (<1.5 V) operation, no significant retention loss after 10(5) s, and no degradation in endurance after 10(4) switching cycles, with stable operation even under a mechanical strain of 0.38%.

Abstract: Electronic devices based on a series of synthesized block copolymers are demonstrated. In particular, a block copolymer system with a lamellar structure exhibits unipolar switching behavior. This study provides a simple strategy based on the adjustment of the block ratio in block copolymers to control the polymer morphology and thus the electrical and switching properties of polymer-based memory devices.

Abstract: A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Abstract: Emerging nonvolatile memory with an oxide-semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The memory is called nonvolatile oxide-semiconductor random access memory (NOSRAM). The memory cell of the NOSRAM (NOSRAM cell) consists of an IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) for data reading, and a cell capacitor for storing charge and controlling the PMOS gate voltage. The IGZO TFT and the cell capacitor are formed over the PMOS. Owing to extremely low-leakage-current characteristics of the IGZO TFT, the charge stored in the 2-fF cell capacitor is maintained for a long time. This long data retention realized innovative nonvolatile memory. The NOSRAM cell fabricated with the 0.8-μ m process technology demonstrated an on/off ratio of 107 and an endurance over 1012 write cycles. In addition, NOSRAM with a memory capacity of 1 Mb was fabricated; the cell size was 12.32 μm2 and the cell array size was 13.5 mm2. The 1-Mb NOSRAM achieved basic operation at 4.5 V or less, write operation at 150 ns/page, read distribution of data “1” with 3σ = 0.10 V, and a data retention over 60 days at 85°C.

Abstract: With conventional memory technologies approaching their scaling limit, the search for a new technology has gained increased attention in the recent years. Resistive RAM (ReRAM), with its superior write latency and energy, small cell size (4F2 for a single level cell, F is the feature size), and support for 3D stacking, has been a promising candidate among emerging memory technologies. A key advantage of ReRAM comes from its non-linear nature, which enables a cross-point array structure without having a dedicated access transistor for each cell.While the cross-point structure is effective in improving the memory density, it has inherent disadvantages which introduce extra design challenges. Based on the device characteristics, we perform a comprehensive analysis of issues related to reliability, energy consumption, area overhead, and performance of the cross-point arrays. In addition to the cell-level analysis, we discuss different programming schemes specifically suited for cross-point arrays. We then study the area, energy, and bandwidth of a 256Mbits ReRAM macro in detail for various write schemes. The simulation results enable designers to identify the most performance/energy/area efficient ReRAM organization and cell parameters that meet specific design goals early in the design stage.