Abstract: We report on world's smallest HfO 2 -based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfO x resistive element stack, with an area of less than 10×10 nm2, fast ns-range on/off switching times at low-voltages and with a switching energy per bit of <0.1pJ. With excellent endurance of more than 5.107cycles, large on/off verified-window (>50), no closure of the on/off window after 30hrs/200C and failure-free device operation after 30hrs/250C thermal stress, the major device-level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability viewpoint, the role of the cap layer and bring insight into the switching mechanisms.

Abstract: We report the observation of ferroelectricity in capacitors based on hafnium-zirconium-oxide. Hf0.5Zr0.5O2 thin films of 7.5 to 9.5 nm thickness were found to exhibit ferroelectric polarization-voltage hysteresis loops when integrated into TiN-based metal-insulator-metal capacitors. A remnant polarization of 16 μC/cm2 and a high coercive field of 1 MV/cm were observed. Further proof for the ferroelectric nature was collected by quasi-static polarization-voltage hysteresis, small signal capacitance-voltage, and piezoelectric measurements. Data retention characteristics were evaluated by a Positive Up Negative Down pulse technique. No significant decay of the initial polarization state was observed within a measurement range of up to two days.

Abstract: Organic molecules and semiconductors have been proposed as active part of a large variety of nonvolatile memory devices, including resistors, diodes and transistors. In this review, we focus on electrically reprogrammable nonvolatile memories. We classify several possible devices according to their operation principle and critically review the role of the π-conjugated materials in the device operation. We propose specifications for applications for organic nonvolatile memory and review the state of the art with respect to these target specifications. Conclusions are drawn regarding further work on materials and device architectures.

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Abstract: A ferroelectric-resistive random access memory consisting of a conductive BiFeO3 epitaxial thin film with a unipolar diode current modulated by electric polarization orientation is reported. This device has a memory that lasts for months, a sufficiently high on current and on/ off ratio to permit ordinary sense amplifiers to measure "1" or " 0", and is fully compatible with complementary metal- oxide semiconductor processing.

Abstract: Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

Abstract: Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

Abstract: Novel nonvolatile universal memory technology is essential for providing required storage for nanocomputing. As a potential contender for the next-generation memory, the recently found "the missing fourth circuit element," memristor, has drawn a great deal of research interests. In this paper, by starting from basic memristor device equations, we develop a comprehensive set of properties and design equations for memristor based memories. Our analyses are specifically targeting key electrical memristor device characteristics relevant to memory operations. Using our derived properties, we investigate the design of read and write circuits and analyze important data integrity and noise-tolerance is sues.

Abstract: Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (V BL-R ) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Abstract: Back-end-of-line integrated 1 × μm2 TiN/HfO2/Ti/TiN MIM memory devices in a 0.25- μm complementary metal-oxide-semiconductor technology were built to investigate the conduction mechanism and the resistive switching behavior as a function of temperature. The temperature-dependent I- V characteristics in fresh devices are attributed to the Poole-Frenkel mechanism with an extracted trap energy level at φ ≈ 0.2 eV below the HfO2 conduction band. The trap level is associated with positively charged oxygen vacancies. The electroformed memory cells show a stable bipolar switching behavior in the temperature range from 213-413 K. The off -state current increases with temperature, whereas the on-state current can be described by a weak metallic behavior. Furthermore, the results suggest that the I-V cycling not only induces significant changes in the electrical properties of the MIM memory devices, i.e., the increase in the off-state current, but also stronger temperature dependence. The temperature effect on the on-state and off-state characteristics is modeled within the framework of the quantum point-contact model for dielectric breakdown using an effective temperature-dependent confinement potential.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

Abstract: Bistable molecules that behave as switches in solution have long been known. Systems that can be reversibly converted between two stable states that differ in their physical properties are particularly attractive in the development of memory devices when immobilized in substrates. Here, we report a highly robust surface-confined switch based on an electroactive, persistent organic radical immobilized on indium tin oxide substrates that can be electrochemically and reversibly converted to the anion form. This molecular bistable system behaves as an extremely robust redox switch in which an electrical input is transduced into optical as well as magnetic outputs under ambient conditions. The fact that this molecular surface switch, operating at very low voltages, can be patterned and addressed locally, and also has exceptionally high long-term stability and excellent reversibility and reproducibility, makes it a very promising platform for non-volatile memory devices.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string

Abstract: Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have defined the fundamental operations that can be performed against storage devices. These three interfaces have endured because the devices within storage subsystems have not fundamentally changed since the invention of magnetic disks. Non-volatile (flash) memory (NVM) has recently become a viable enterprise grade storage medium. Initial implementations of NVM storage devices have chosen to export these same disk-based seek/read/write interfaces because they provide compatibility for legacy applications. We propose there is a new class of higher order storage primitives beyond simple block I/O that high performance solid state storage should support. One such primitive, atomic-write, batches multiple I/O operations into a single logical group that will be persisted as a whole or rolled back upon failure. By moving write-atomicity down the stack into the storage device, it is possible to significantly reduce the amount of work required at the application, filesystem, or operating system layers to guarantee the consistency and integrity of data. In this work we provide a proof of concept implementation of atomic-write on a modern solid state device that leverages the underlying log-based flash translation layer (FTL). We present an example of how database management systems can benefit from atomic-write by modifying the MySQL InnoDB transactional storage engine. Using this new atomic-write primitive we are able to increase system throughput by 33%, improve the 90th percentile transaction response time by 20%, and reduce the volume of data written from MySQL to the storage subsystem by as much as 43% on industry standard benchmarks, while maintaining ACID transaction semantics.

Abstract: We present a voltage-scalable and process-variation resilient, hybrid memory architecture, suitable for use in MPEG-4 video processors such that power dissipation can be traded for graceful degradation in “quality.” The key innovation in our proposed work is a hybrid memory array, which is a mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that the human visual system is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show that under iso-area condition, we can obtain at least 32% power savings in the hybrid memory array compared to the conventional 6T SRAM array.

Abstract: Phase-change memory (PCM) has emerged as one among the most promising technologies for next-generation nonvolatile solid-state memory. Multilevel storage, namely storage of non-binary information in a memory cell, is a key factor for reducing the total cost-per-bit and thus increasing the competitiveness of PCM technology in the nonvolatile memory market. In this paper, we present a family of advanced programming schemes for multilevel storage in PCM. The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energy-per-bit and cell storage capacity. Experimental results from PCM test-arrays are presented to validate the proposed programming schemes. In addition, the reliability issues of multilevel PCM in terms of resistance drift and read noise are discussed.

Abstract: Lack of a suitable selection device to suppress sneak current has impeded the development of 4F2 crossbar memory array utilizing stable and scalable bipolar resistive-switching. We report a high-performance nonlinear bipolar selector realized by a simple Ni/TiO 2 /Ni MIM structure with a high current density of 105 A/cm2, and a Ni/TiO 2 /Ni/HfO 2 /Pt vertically stacked 1S1R cell capable of gigabit memory implementation. Furthermore, the demonstration of 1S1R array fabricated completely at room temperature on a plastic substrate highlights the promise of future extremely low-cost flexible nonvolatile memory.

Abstract: Plastic-substrate-based electronic devices are attractive because of their inherit merits of low cost, light weight, environmentally friendly low temperature processing, and the application in fl exible displays and integrated circuits (ICs). Fast progress of logic ICs using thin-fi lm transistors (TFT) on plastic has been demonstrated. However, one fundamental challenge for plastic electronics is the lack of good performance non-volatile memory (NVM) devices. [ 1–5 ] This is due to the degraded dielectric quality of charge-based fl ash (CTF) memory from the limited low temperature process. [ 2 ] Alternatively, the resistive random access memory (RRAM) [ 6–21 ] shows promising NVM performance on plastic even when processed at low temperature, but the large set and reset currents are the basic limitation for high-density and low-power operation. In addition, the large switching energies degrade the endurance due to excessive stress. In this paper, record high-performance NVM has been demonstrated on low cost polyimide substrate. A very low set current of 1.6 μ A at 3 V (4.8 μ W) and reset current of −0.5 nA at −2 V (1 nW) were needed to reach the bistable resistance state, which led to a large memory window with a highto low-resistance state ratio (HRS/LRS) of 9 × 10 2 . Additionally, good retention was obtained with a small HRS/LRS decay from the initial 9 × 10 2 to 7 × 10 2 at 85 ° C for 10 4 s. Furthermore, excellent endurance of 10 5 cycles was measured at a very fast 50 ns switching time. This is the lowest reported switching power NVM on plastic with excellent 10 5 cycling endurance and good retention. The excellent NVM performance on fl exible plastic is due to the using novel ultra-low power hopping conduction mechanism [ 22 ] rather than the conductive fi lament in conventional RRAM. [ 17 , 18 ] This new RRAM device sets a new standard for NVM performance on low-cost fl exible substrates.

Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract: A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.

Abstract: A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.

Abstract: Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.

Abstract: We report on the nonvolatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly(N-vinylcarbazole) (PVK) colloids hybrid layer deposited on flexible poly(ethyleneterephthalate) (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C−V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ±3 V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as 1 × 105. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above 1.5 × 105 cycles, and a high ON/OFF ratio of ∼105 could be achieved consistently even after quite a long retention time of more than 1 × 106 s. To clarify the memory mechanism of the hole-mediated bistable organic memory device, the interactions between Au nanoparticles and poly(N...

Abstract: A non-volatile storage subsystem regulates energy consumption by controlling or “throttling” the rate at which memory operations are performed. During relatively idle periods in which few or no memory operations are performed, energy allotments or “counts” are accumulated to reflect unused energy. These accumulated energy counts may then be effectively allocated for use during bursts or other periods of relatively heavy memory activity, such that the memory operations are performed at a relatively high rate without causing a maximum average power consumption to be exceeded.

Abstract: With recent progress in material science, resistive random access memory (RRAM) devices have attracted interest for nonvolatile, low-power, nondestructive readout, and high-density memories. Relevant performance parameters of RRAM devices include operating voltage, operation speed, resistance ratio, endurance, retention time, device yield, and multilevel storage. Numerous resistive-switching mechanisms, such as conductive filament, space-charge-limited conduction, trap charging and discharging, Schottky Emission, and Pool-Frenkel emission, have been proposed to explain the resistive switching of RRAM devices. In addition to a discussion of these mechanisms, the effects of electrode materials, doped oxide materials, and different configuration devices on the resistive-switching characteristics in nonvolatile memory applications, are reviewed. Finally, suggestions for future research, as well as the challenges awaiting RRAM devices, are given.

Abstract: The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Green's function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines (330) from the substrate through the multiple layers of planes which together with arrays of word lines (340) on each plane are used to access the memory elements. The memory elements (342, 344) of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, diode (332) is formed in series with each memory element (342, 344) to reduce current leakage. The diode (332) is incorporated within a pillar line (330) acting as a bit line without taking up additional space.