Showing papers on "Non-volatile memory published in 2003"
21 May 2003
TL;DR: The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible and an insight into the multilevel approach, where two bits are stored in the same cell, is presented.
Abstract: This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.
1,058 citations
8 Dec 2003
TL;DR: The scaling projection shows that there is no physical limit to scaling down to the 22 nm node, with a number of technical challenges being identified.
Abstract: With the increasing challenge of scaling floating gate nonvolatile memory technology to beyond 65 nm, alternative memory technologies are being investigated Chalcogenide based phase change memory (R Neale et al, Electronics, p56-60, 1970) is one of the alternative memory candidates In this review, the physics and operation of phase change memory are first presented, followed by a discussion of the current status of development Finally, the scaling capability of the technology is presented The scaling projection shows that there is no physical limit to scaling down to the 22 nm node, with a number of technical challenges being identified
671 citations
21 May 2003
TL;DR: How the memory operates is described, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled the recent demonstration of a 1-Mbit memory chip.
Abstract: Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.
512 citations
Patent•
28 Jul 2003
TL;DR: In this article, the authors describe an electronic system for a memory system and its controller within a single memory card, where the cards utilize a main circuit board with a plurality of sub-boards attached on both sides, each sub-board carrying several integrated circuit chips.
Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.
448 citations
Patent•
10 Sep 2003TL;DR: In this article, a data structure in a non-volatile memory includes a first indicator that provides an indication of a number of times a first block of a plurality of blocks in a NVRAM has been erased.
Abstract: Methods and apparatus for storing erase counts in a non-volatile memory of a non-volatile system are disclosed. According to one aspect of the present invention, a data structure in a non-volatile memory includes a first indicator that provides an indication of a number of times a first block of a plurality of blocks in a non-volatile memory has been erased. The data structure also includes a header that is arranged to contain information relating to the blocks in the non-volatile memory.
336 citations
Patent•
2 Oct 2003TL;DR: In this article, a method for reducing source line bias is proposed by read/write circuits with features and techniques for multi-pass sensing, where each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value.
Abstract: A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
321 citations
Patent•
9 Oct 2003TL;DR: In this article, a method for wear leveling in a nonvolatile memory system is described, which includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory elements and associating the contents of the first element with the second element.
Abstract: Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.
290 citations
Patent•
31 Mar 2003
TL;DR: In this paper, an apparatus for cooling a skin surface includes an RF device that has an RF electrode with dielectric and conductive portions, and a cooling member is coupled to the RF device.
Abstract: An apparatus for cooling a skin surface includes an RF device that has an RF electrode with dielectric and conductive portions. The RF device is configured to be coupled to an RF energy source. A cooling member is coupled to the RF device. A memory is coupled to the RF device. The memory is configured to store information to facilitate operation of at least one of the RF electrode, the cooling member, and the RF energy source.
285 citations
Patent•
5 Mar 2003TL;DR: In this article, the channel potential of the source side of the NAND string is increased to avoid program disturb by applying a voltage (e.g. Vdd) to the source contact and turning on the source-side select transistor for the nAND sting corresponding to the cell being inhibited.
Abstract: A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.
254 citations
Patent•
13 Feb 2003TL;DR: In this article, the authors propose to use a non-volatile memory system without incurring additional data transfer latency by transferring data from a controller to a second memory chip and a programming operation is caused to begin in that chip.
Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.
230 citations
Patent•
20 Jun 2003TL;DR: In this article, a memory cell array in which electrically rewritable floating gate type memory cells are arranged, and a plurality of sense amplifier circuits configured to read data from the memory cell arrays are presented.
Abstract: A non-volatile semiconductor memory device includes: a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and a plurality of sense amplifier circuits configured to read data from the memory cell array, wherein each the sense amplifier circuit is configured to sense cell data of a first memory cell selected from the memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to the first memory cell and written after the first memory cell.
Patent•
16 Oct 2003
TL;DR: In this paper, a combination of EEPROM and flash memory is described, in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EPROM cell.
Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells The EEPROM cells are erased by byte while the Flash cells erased by block The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation
TL;DR: In this paper, the operation of a potential nonvolatile bistable capacitor memory element consisting of a metal gate, a 170 nm thick ferroelectric Langmuir-Blodgett film of vinylidene fluoride (70%) with trifluoroethylene (30%) copolymer, and a 100 nm thick silicon-oxide insulating layer, all deposited on an n-type silicon semiconductor substrate.
Abstract: We report the operation of a potential nonvolatile bistable capacitor memory element consisting of a metal gate, a 170 nm thick ferroelectric Langmuir–Blodgett film of vinylidene fluoride (70%) with trifluoroethylene (30%) copolymer, and a 100 nm thick silicon-oxide insulating layer, all deposited on an n-type silicon semiconductor substrate. The device exhibited clear capacitance hysteresis as the gate voltage was cycled between ±25 V, with a capacitance dynamic range of 8:1 and threshold voltage shift of 2.8 V. The results are in good agreement with the model of Miller and McWhorter [J. Appl. Phys. 72, 5999 (1992)].
Patent•
30 Sep 2003TL;DR: In this article, the first and second Y-line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit.
Abstract: Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
TL;DR: In this article, the write/erase characteristics of Germanium nanocrystal memory device were modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects, and a trap model was proposed to describe the retention characteristic of the memory.
Abstract: The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.
8 Dec 2003
TL;DR: This new technique controls the threshold voltage of the chalcogenide storage device by varying the height and duration of the write pulse, which achieves the requirement of non-volatility, fast writing/reading, random access, high scalability, compact cell size, and low cost.
Abstract: A new concept for non-volatile memory is demonstrated. This new technique controls the threshold voltage of the chalcogenide storage device by varying the height and duration of the write pulse. Consequently, the chalcogenide device serves as both the access element and the memory element. Therefore, it does not need any access transistor in the memory array. The new memory achieves the requirement of non-volatility, fast writing/reading, random access, high scalability, compact cell size, and low cost.
Patent•
9 Dec 2003TL;DR: In this article, an error recovery technique is used on marginal nonvolatile memory cells, which shifts the voltage threshold of the marginal memory cells to a positive value by biasing adjacent memory cells.
Abstract: An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.
Patent•
28 Nov 2003
TL;DR: In this article, the authors proposed a nonvolatile memory device with a function of finishing the write time upon receiving an operation signal outputted from a power source voltage detecting circuit.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile memory device having a function of finishing the write time upon receiving an operation signal outputted from a power source voltage detecting circuit or finishing the write time while shortening the write time than a desired write time SOLUTION: The operation of a timer circuit is controlled by an operation signal outputted from a power source voltage detecting circuit, an erase cycle time and a write cycle time can be shortened without changing a discharge cycle time Thereby, a required time can be secured in a discharge cycle even if write is interrupted by a detecting signal of the power source voltage detecting circuit in an EEPROM, electric charges charged up in column lines or bit lines provided in a nonvolatile memory array can be discharged surely COPYRIGHT: (C)2004,JPO
Patent•
18 Sep 2003
TL;DR: A nonvolatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read and write circuits to a minimum as discussed by the authors.
Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.
Patent•
19 Jul 2003TL;DR: In this paper, a nonvolatile memory element and associated production methods and memory element arrangements are presented, where a changeover material and a first and second electrically conductive electrodes are present at the changeover materials.
Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
Patent•
18 Mar 2003TL;DR: In this paper, a programmable resistance memory device (PRSM) is defined, which includes a semiconductor substrate, at least one cell array, and a read/write circuit formed on the substrate as underlying the cell array for data reading and data writing.
Abstract: programmable resistance memory device includes: a semiconductor substrate; at least one cell array, in which memory cells are arranged, formed above the semiconductor substrate, each the memory cell having a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner, the access element having such a resistance value in an off-state in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.
Patent•
18 Sep 2003TL;DR: In this paper, the bit line voltages of the plurality of bit line coupled to the memory cells are controlled such that the voltage difference between each adjacent pair of lines is substantially independent of time while their conduction currents are being sensed.
Abstract: A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are controlled such that the voltage difference between each adjacent pair of lines is substantially independent of time while their conduction currents are being sensed. When this condition is imposed, all the alternate currents due to the various bit line capacitance drop out since they all depend on a time varying voltage difference. In another aspect, sensing the memory cell's conduction current is effected by noting its rate of discharging a dedicated capacitor provided in the sense amplifier.
Patent•
20 Mar 2003
TL;DR: In this article, a nonvolatile memory is provided with a memory cell 6 constituted of a floating gate and a control gate and memory cell selection transistor 2, a reference cell 12 constituted of reference cell transistor 30 having the same structure as the memory cell transistor 1 and a reference-cell selection transistor 8 and a Reference wordline potential generating circuit 31 connected to a gate of the reference cell selector transistor 8.
Abstract: PROBLEM TO BE SOLVED: To realize low power consumption and stable readout operation in a wide range of power source potential in a nonvolatile memory using a differential type sense amplifier. SOLUTION: The nonvolatile memory is provided with a memory cell 6 constituted of a memory cell transistor 1 having a floating gate and a control gate and a memory cell selection transistor 2, a reference cell 12 constituted of a reference cell transistor 30 having the same structure as the memory cell transistor 1 and a reference cell selection transistor 8 and a reference wordline potential generating circuit 31 connected to a gate of the reference cell selection transistor 8. The same power source voltage is applied between the floating gate and a source node of the reference cell transistor 30 at the time of readout and the intermediate potential between the potential applied at the time when the memory cell selection transistor 2 is selected and the potential applied at the time of non-selection is applied to the gate of the reference cell selection transistor 8. COPYRIGHT: (C)2006,JPO&NCIPI
Patent•
28 Feb 2003TL;DR: In this paper, a system and method for booting a computing device using a NAND flash memory is described, where the boot code stored in the NAND Flash memory is transferred to a RAM for execution by the CPU.
Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.
1 Dec 2003
TL;DR: In this article, a new non-volatile memory with extremely high density metal nano-dots, MND (metal nano-dot) memory, was proposed and fundamental characteristics of the MND memory were evaluated.
Abstract: A new non-volatile memory with extremely high density metal nano-dots, MND (metal nano-dot) memory, was proposed and fundamental characteristics of the MND memory were evaluated The MND film is used as a charge retention layer in the MND memory The MND film consists of a thin oxide film that dispersively includes high density metal dots with nano-scale The MND film is formed by using sputtering technique with a special sputtering target The size and the density of the MND in the film are typically 2-3 nm and around 2/spl times/10/sup 13//cm/sup 2/, respectively, which were superior to that of Si quantum dot memory Non-volatile memory operation at a relatively low voltage and good endurance characteristic were confirmed in the MND memory fabricated according to the conventional MOS process
Patent•
27 Feb 2003
TL;DR: In this paper, a data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array.
Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and programming operation performed in a short time can be realized.
Patent•
24 Jun 2003TL;DR: In this article, a memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivities type, whereby said first and said second junction regions are part of respectively the first and second bitline.
Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
8 Dec 2003
TL;DR: In this article, FD-SOI FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm.
Abstract: FD-SOI (fully depleted silicon-on-insulator) FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm Although the FinFET SONOS device does not have a body contact, excellent program/erase characteristics are achieved, together with high endurance, long retention time and low reading disturbance Devices fabricated on [100] and [110] silicon surfaces are compared
TL;DR: In this article, the authors compared simulated write/erase characteristics of nonvolatile memory with different oxides SiO 2, Al 2 O 3 and ZrO 2 as a top dielectric.
Abstract: The comparison of simulated write/erase characteristics of silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memory with different oxides SiO 2 , Al 2 O 3 and ZrO 2 as a top dielectric was made. We demonstrate, that an application of high- k dielectrics allows to decrease the write/erase programming voltage amplitude or programming time from 1 ms to 10 μs. The ZrO 2 suppresses parasitic electron injection from polysilicon gate. Also the design of SONOS memory based on high- k dielectrics is promising for terabit scale using hot carriers injection EEPROM and DRAM memory.
10 Jun 2003
TL;DR: In this paper, a scalable, low power, deep submicron TFT-SONOS memory cell is described with characteristics rivaling those of single crystal devices (>10/sup 6/ cycles, /spl sim/1.6 V window after 10 years on cycled cell at 85 C).
Abstract: For the first time, a scalable, low power, deep-submicron TFT-SONOS (Thin-Film Transistor Silicon-Oxide-Nitride-Oxide-Silicon) memory cell is described with characteristics rivaling those of single crystal devices (>10/sup 6/ cycles, /spl sim/1.6 V window after 10 years on cycled cell at 85 C) showing the promise of 3D integration and ultra-small cell footprints. The ability to vertically stack device layers enables the current memory density record of /spl sim/200 Mbyte/cm/sup 2/, set by 90 nm NAND, to be surpassed.