Abstract: A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

Abstract: Introduced the concept of floating-gate interference in flash memory cells for the first time The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells It results from capacitive coupling via parasitic capacitors around the floating gate The coupling ratio defined in the previous works should be modified to include the floating-gate interference In a 012-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 02 V shift in multilevel cell operation Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors

Abstract: In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.

Abstract: The development status of Ovonic Unified Memory (OUM), a phase-change non-volatile semiconductor memory technology for VLSI stand-alone memory and embedded applications, is discussed. Using 0.18 μm 3 V CMOS, cells from 5F/sup 2/ to 8F/sup 2/ are built in a charge-pump-free 4 Mb development vehicle. Direct overwrite, 10 ns reset times, 50 ns set times, and 1.0×10/sup 12/ cycling are achieved. At en-year data retention is projected at 120°C.

Abstract: Flash memory is now a critical component in building embedded or portable devices because of its nonvolatile, shock-resistant, and power-economic nature. With the very different characteristics of flash memory, mechanisms proposed for many block-oriented storage media cannot be directly applied to flash memory. Distinct from the past work, we propose an adaptive striping architecture to significantly boost the system performance. The capability of the proposed mechanisms and architecture is demonstrated over realistic prototypes and workloads.

Abstract: A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines

Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.

Abstract: Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive states upon application of voltage pulses and the non-ohmic device imparts a relatively high resistance to the memory plug upon application of low magnitude voltages.

Abstract: The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

Abstract: A novel non-volatile memory is disclosed. The non-volatile memory including an array of data storage cells that individually include a storage element (43) such as a floating gate, a control gate and first and second source/drain terminals. A current source (61) provides a current to the first source/drain terminal of the data storage element. A node (75) is electrically connected to the second source/drain terminal of the data storage element. A bias circuit (73, 69) provides a bias voltage to the node. The bias voltage varies with temperature in a manner approximately inverse to the thermal variation of the threshold voltage of the data storage element. A control gate voltage circuit provides a voltage level to the control gate of the data storage cell.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: Methods and devices for monitoring distributed electric power are disclosed, including energy devices with a sensor for monitoring an electric circuit, and a memory to store sensor measurements. Various techniques are disclosed for using polymeric RAM, 1T-DRAM, enhanced SRAM, magnetoresistive RAM, organic RAM, chalcogenide RAM, holographic memory, PLEDM, single-electron RAM, fractal cluster glass memory and other technologies in energy devices with high-endurance, high-density, high-capacity, non-volatile, solid-state, or removable memories.

Abstract: A well-known effect in flash memories is stress-induced leakage in a small fraction of memory cells after program/erase cycling. This paper presents a comprehensive statistical reliability model with an excellent fit to data collected on several technology generations in multi-year bakes. The leakage current is exponential in voltage and has a low but nonzero activation energy. The statistical variation is Weibull. The fraction of cells affected scales as a power law in cycle count, with significant dependence on the vertical and horizontal electric fields in cycling but little on the cycling temperature. A single model equation comprehends all of these effects. The mechanism anneals or recovers at moderate temperatures in a manner sensitive to processing details, which are discussed. A new technique is introduced to deduce the number of traps involved in the trap-assisted-tunneling (percolation) paths by correlating the effect to oxide trap density using cycling-induced erase-time push-out. The results suggest that the percolation paths consist of only a small number of traps, most likely two. Contrary to predictions that this mechanism is a hard barrier to scaling of flash memory, we show that it has been possible to reduce the effect by several orders of magnitude over the course of several generations of technology scaling.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

Abstract: A memory system including an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level. And a method of controlling the operation of a memory system which comprises an array of memory cells, the method comprising the steps of providing a first programming voltage, initiating a memory programming operation if the first programming voltage magnitude exceeds a first voltage level, continuing the initiated programming operation if the first programming voltage remains greater in magnitude than a second voltage level, with the first voltage level magnitude being greater in magnitude than the second voltage level, and terminating the initiated programming operation if the first programming voltage magnitude drops below the second voltage level.

Abstract: A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.

Abstract: A method (1110 a ;1110 b) of refreshing an electrically erasable and programmable non-volatile memory (100) having a plurality of memory cells (Mhk) is proposed. The method includes the steps of: verifying (1106-1114; 1152-1162) whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or voltage range), and individually restoring (1116-1130) the correct condition of the memory cell if the result of the verification is positive.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate Therefore, a nonvolatile memory capable of miniaturization can be provided

Abstract: A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

Abstract: A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.

Abstract: A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Abstract: An array of memory cells of an integrated circuit are organized so metal bitlines are segmented. The memory cells may be nonvolatile memory cells such as floating gate, Flash, EEPROM, and EPROM cells. The bitlines for the memory cells are strapped to metal, and the metal bitline is segmented. The individual segments may be selectively connected to voltages as desired to allow configuring (e.g., programming) or reading of the memory cells. The programming voltage may be a high voltage, above the VCC of the integrated circuit. By dividing the metal bitlines into segments, this reduces noise between bitlines and improve the performance and reliability, and reduce power consumption because the parasitic capacitances are reduced compared to a long metal bitline (i.e., where all the segments are connected together and operated as one).

Abstract: A memory device includes a plurality of memory elements each having: an antiferromagnetic layer, a first pinned layer coupled to the antiferromagnetic layer, a nonmagnetic spacer layer coupled to the first pinned layer, a second pinned layer coupled to the spacer, and a free layer coupled to the second pinned layer A plurality of single wiring circuits are provided, each wiring circuit being coupled to a memory element An addressing mechanism applies current pulses to the memory elements via the single wiring circuits for writing to the memory elements The addressing mechanism also applies a sense current to the memory elements via the single wiring circuits for reading the memory elements

Abstract: Developments in portable communication and computing systems are creating a growing demand for nonvolatile random access memory that is dense and fast. None of the existing solid-state memories can provide all the needed attributes in a single memory solution. Therefore, to achieve the required multiple functionality requirements, a number of different memories are being used while compromising performance and adding cost to the system. Magnetoresistive Random Access Memory (MRAM) has the potential to replace these memories in various systems with a single, universal memory solution. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. In addition, MRAM can operate at high-speed and is expected to have competitive densities. In this paper we describe several fundamental technical and scientific aspects of MRAM with emphasis on recent accomplishments that enabled our successful demonstration of a 256 kbit memory chip.

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Abstract: A nonvolatile semiconductor memory device having a plurality of digit lines (GBL) to which a plurality of nonvolatile memory cells (MC) are connected and a data line (LDB) connected selectively to the digit line (GBL), the nonvolatile semiconductor memory device further comprising: a first data line (LDB) to which the selected nonvolatile memory cell (MC) is connected through the digit line (LDB) and through which a current based on memory cell information flows; a second data line (LDB) through which a reference current (Iref) flows; and a current comparing portion (D) to which the first and second data lines (LDB) are connected and which compares a current based on the memory cell information with the reference current (Iref), wherein the current comparing portion (D) includes a current load portion (52A) having a current mirror structure and a connection changing portion (QD0 to QD3) for changing a connection between the first and second data lines (LDB) and the current load portion (52A).

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 A thickness or less, as commonly available, from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: A method of selectively programming an individual memory cell of a non-volatile memory array. The non-volatile memory array is an array of memory cells. Each memory cell is made up of an ONO gate built on a substrate, which also acts as a well. On one side of the gate is a diffusion drain encompassed by a localized well region set in the well. On the other side of the gate is a diffusion source set in the well. When operated, appropriate voltages are applied to the source, the gate, the drain, and the localized well region to program or erase the non-volatile memory. The designed localized well region prevents an induction current in the unselected gates of the array, allowing for better selectivity and performance.