Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Abstract: A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

Abstract: Scaling the programming voltage, while still maintaining 10-year data retention time, has always been a big challenge for polysilicon–oxide–nitride–oxide–silicon (SONOS) researchers. We describe progress in the design and scaling of SONOS nonvolatile memory devices. We have realized −9+10 V (1 ms) programmable SONOS devices ensuring 10-year retention time after 107 erase/write cycles at 85°C. Deuterium anneals, applied in SONOS device fabrication for the first time, improves the endurance characteristics when compared with traditional hydrogen or forming gas anneals. We introduce scaling considerations and process optimization along with experiments and SONOS device characterization. A field programmable gate array-based measurement system is described for the dynamic characterization of SONOS nonvolatile memory devices.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Abstract: A secure software package for original equipment manufacturers to run in electronic devices in order to access and dynamically decrypt encrypted audio video or other content from a memory storage device such as a memory card, optical or hard disk such that the user interface of the device need only send simple commands and the decrypted content is output.

Abstract: A non-volatile memory system, such as a flash EEPROM system, is disclosed to be divided into a plurality of blocks and each of the blocks into one or more pages, with sectors of data being stored therein that are of a different size than either the pages or blocks. One specific technique packs more sectors into a block than pages provided for that block. Error correction codes and other attribute data for a number of user data sectors are preferably stored together in different pages and blocks than the user data.

Abstract: The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.

Abstract: A ferroelectric non-volatile memory (100, 436) comprising: a plurality of memory cells (14, 116, 117, 118, 119), each containing an FeFET (40, 140A) and a MOSFET (20, 120A), each of said FeFETs (14) having a source (42), a drain (44), a substrate (45), and a gate (58), and each MOSFET (20) having a pair of source/drains (22, 23) and a gate (21). The cells are arranged in an array comprising a plurality of rows (180) and a plurality of columns (184). A gate line (132) and a bit line (134) are associated with each column, and a word line (136), a drain line (139), and a substrate line (138) are associated with each row. A read MOSFET (160) is connected between a drain input (137) and the drain line associated with each row. The gate (165) of the read MOSFET is connected to an input for the read enable signal.

Abstract: A data storage device is disclosed that comprises a cross-point memory array formed on a dielectric substrate material. The cross-point memory array comprises first and second sets of transverse electrodes separated by a storage layer including at least one semiconductor layer. The storage layer forms a non-volatile memory element at each crossing point of electrodes from the first and second sets. Each memory element can be switched between low and high impedance states, representing respective binary data states, by application of a write signal in the form of a predetermined current density through the memory element. Each memory element includes a diode junction formed in the storage layer, at least whilst in the low impedance state. A plurality of the data storage devices can be stacked and laminated into a memory module providing inexpensive high capacity data storage. Such a memory module can be employed in an archival data storage system in which the memory module provides a write-once data storage unit receivable in an appliance or interface card.

Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Abstract: Unipolar devices constructed from ferromagnetic semiconducting materials with variable magnetization direction are shown theoretically to behave very similarly to nonmagnetic bipolar devices such as the p-n diode and the bipolar (junction) transistor. Such devices may be applicable for magnetic sensing, nonvolatile memory, and reprogrammable logic.

Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Abstract: An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Abstract: A method for programming an NROM cell which includes the steps of applying a drain (VD), a source (VS) and a gate voltage (VG) to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: A non-volatile memory comprising a semiconductor active layer provided on an insulating substrate, an insulating film provided on the semiconductor active layer, a floating gate electrode provided on the insulating film, an anodic oxidized film obtained by anodic oxidation of the floating gate electrode, and a control gate electrode provided in contact with the anodic oxidized film, and a semiconductor device, particularly a liquid crystal display device comprising the non-volatile memory.

Abstract: A network storage device In one embodiment, the network storage device of the present invention uses solid-state non-volatile memory (eg, flash-memory) as a storage medium, and has at least one interface configured for coupling to a computer network The network storage device of the present invention is accessible to client(s) and/or server(s) of the computer network, and uses solid-state non-volatile memory to store data received therefrom The network storage device may also be configured to include a memory for caching data to be written to the solid-state non-volatile memory In order to provide additional storage, the network storage device may also include a peripheral interface or another network interface for coupling to a mass storage device (eg, a RAID system), and/or another network interface for coupling to a network of mass storage devices The network storage device may be a stand-alone unit, or may be implemented as part of a network server, or as part of a mass storage device

Abstract: Chalcogenide is a proven phase change material used in re-writeable CDs and DVDs. This material changes phases, reversibly and quickly, between an amorphous state that is dull in appearance and electrically high in resistance, and a polycrystalline state that is highly reflective and low in resistance. The application of this commercially proven technology to create semiconductor memories is discussed. The successful results of an effort to create a memory cell that would allow for the production of a dense, low power, non-volatile memory is presented.

Abstract: Ferroelectric random access memories (FRAMs®) are nonvolatile integrated circuit memories that store data by using the field switchable polarization state of a ferroelectric material. Besides allowing unique applications, FRAM memories are ideal replacements for standard random access memory, erasable programmable read-only memory, and Flash memories due to their fast access speed, low power consumption, extended read/write endurance, and ability to store data without the need for battery backup power. FRAM memories have been mass produced since 1992 and memory densities up to 256 kbit are currently available for purchase. Current applications include smart cards, data collection and storage (e.g., power meters), configuration storage, and buffers. The ferroelectric material at the core of FRAM is perovskite PbZr1−xTixO3 (PZT). Current FRAM cell designs utilize the PZT in a bistable capacitor structure that is integrated with a transistor or a complementary capacitor and two transistors. A review of ferroelectric performance in current memory products will be presented. Recent development has lead to capacitor performance with endurance beyond 1012 read/write cycles and operation at 1.8 V. A roadmap for future FRAM development will be presented.Ferroelectric random access memories (FRAMs®) are nonvolatile integrated circuit memories that store data by using the field switchable polarization state of a ferroelectric material. Besides allowing unique applications, FRAM memories are ideal replacements for standard random access memory, erasable programmable read-only memory, and Flash memories due to their fast access speed, low power consumption, extended read/write endurance, and ability to store data without the need for battery backup power. FRAM memories have been mass produced since 1992 and memory densities up to 256 kbit are currently available for purchase. Current applications include smart cards, data collection and storage (e.g., power meters), configuration storage, and buffers. The ferroelectric material at the core of FRAM is perovskite PbZr1−xTixO3 (PZT). Current FRAM cell designs utilize the PZT in a bistable capacitor structure that is integrated with a transistor or a complementary capacitor and two transistors. A review of ferro...

Abstract: The preferred embodiments described herein provide a memory device and method for sensing while programming a non-volatile memory cell. In one preferred embodiment, a memory device is provided with a memory cell and a detection circuit. While the memory cell is being programmed, the detection circuit determines whether the memory cell is in a programmed state. If the memory cell is in a programmed state, the programming of the memory cell is terminated. As compared with prior programming approaches, this preferred embodiment reduces programming time and power while increasing programming bandwidth (the number of memory cells that can be programmed per unit time). In another preferred embodiment, a plurality of memory cells along a wordline are programmed simultaneously. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The present invention provides a memory device including a storage medium (102) which is disposed in a number of storage location (104). Each storage location (104) is addressed by a working electrode (101) and a reference electrode (103) so that the storage medium (102) combined with the electrodes form a storage cell (100) in each storage location (104). The memory device of the present invention also incorporating winged trimmers of porphyrinic macrocycles. In the preferred embodiments, the two wing porphyrinic macrocycles are the dame, and both are different from the center macrocycle. Such molecules are relatively easy to synthesize, have four different and distinguishable oxidation states, and thus provide molecules, information storage media and apparatus that store two bits of information.

Abstract: The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

Abstract: The present invention includes a 6F 2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

Abstract: To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

Abstract: A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions (pinning regions) are formed in a channel length direction. The pinning regions suppress the spread of a depletion layer of a drain region, and a short channel effect caused by fine processing. Furthermore, in a memory transistor using pinning regions, by assigning one value or one bit of data to each channel forming region, the memory transistor is allowed to have multi values. More specifically, the present invention has a configuration in which a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential can be applied independently to a plurality of pinning regions.

Abstract: A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.