Abstract: PbTiO3 thin films with good ferroelectric properties have been prepared by rf sputtering at relatively low temperatures of ∼350 °C and subsequent laser annealing. The annealing has been done by cw CO2 laser irradiation at 10∼40 W for 0.1∼10 sec. A distinct phase change from the paraelectric Pyrochlore phase to the ferroelectric perovskite phase is induced by means of a solid‐state reaction in the irradiated region without temperature rise of peripheral regions. The observed effect increases feasibility of producing new functional electronic devices employing ferroelectric thin films such as nonvolatile memory field‐effect transistors, infrared optical field‐effect transistors, and imaging devices with a ferroelectric layer.

Abstract: This paper has discussed a number of E2PROM failure mechanisms for both erase/write cycling and data retention. It has been shown that Fowler-Nordheim tunneling used for programming does not affect data retention. Erase/write cycling has been shown to degrade device margins by only a small amount and is easily guardbanded. Erase/write cycling does contribute to a significant portion of the observed failure rate due to oxide breakdown under high field operation. Defect related charge loss has been shown to be similar to that observed in EPROMs. Finally, it has been shown that E2PROMs can perform reliably in applications requiring up to 10,000 erase/write cycles per byte.

Abstract: A completely TTL-compatible, single 5V supply, nonvolatile RAM utilizing a three-layer polysllicon process and a low-current floating-gate tunneling approach, will be described.

Abstract: This paper will discuss an 18ns/150mW fully static 4096×1b RAM, using double poly HI-CMOSII technology with 2μm gate length.

Abstract: An electronic postage meter having an accounting section including a nonvolatile memory (NVM), computer means for reading the condition of the nonvolatile memory during a power-up cycle of the meter, and means in the meter for storing any signal which results from the reading of the nonvolatile memory by the computer means. In accordance with further aspects of the present invention, a method is provided for determining that an electronic postage meter has a weak nonvolatile memory, a data center and service department are adapted to receive signals from the meter indicating a weak nonvolatile memory, and an intercommunication system is established between the data center to receive signals from the meter indicating a weak nonvolatile memory.

Abstract: A nonvolatile memory cell employing a bistable RAM cell and an electrically erasable and electrically programmable (E 2 ) floating gate memory device. The E 2 cell is coupled between one of the input/output nodes of the RAM cell and a clear/recall line. The loads of the RAM cell are imbalanced, causing this cell to assume a predetermined state. If the E 2 cell is in its erased state after a storage cycle, the potential on the store/recall line causes the RAM cell to assume its other stable state on recall.

Abstract: An electronic postage meter includes a memory protection circuit. The memory protection circuit prevents the inadvertent writing of spurious data into memory locations in the nonvolatile memory during a power down cycle. The memory protection circuit works in conjection with a WRITE voltage terminal associated with the nonvolatile memory. Means couple a first voltage source providing a predetermined polarity voltage to the WRITE voltage terminal when a predetermined power condition exists such that the nonvolatile memory is enabled to have data written into memory locations. When the predetermined power condition does not exist, the means utilize a second different voltage source to change the voltage level at the WRITE voltage terminal to insure that data is not written into the memory locations.

Abstract: A small ferroelectric ceramic element is used with an insulating gate transistor and two diodes as an electrically addressed, nonvolatile memory device which is read out nondestructively. The device uses the anomalous photovoltaic effect in ferroelectric ceramics, an effect in which the polarity and magnitude of photovoltages depend on the direction and magnitude of remanent polarization. Experimental results give memory characteristics. The device could be programmed with pulses as short as 200 ns. There is long-time retention of stored data.

Abstract: The threshold voltage shift of various dual-electron-injector structures (DEIS's) which are composed of chemically vapor-deposited (CVD) stacks of Si-rich SiO 2 , SiO 2 , and Si-rich SiO 2 incorporated into floating polycrystalline-silicon-gate electrically alterable read-only memories (EAROM's) has been studied as a function of write/erase voltages, write/erase times, and the initial charge state of the floating poly-Si gate and compared, to a simple physical model for a variety of different device structures. This model depends on the interface limited (Si-rich-SiO 2 -SiO 2 interfaces) enhanced current injection observed for the dual-electron-injector stacks at moderate gate voltages for both voltage polarities, the changing electric fields in the SiO 2 layers as the floating polycrystalline silicon gate electrode is charged or discharged, and the voltage-dependent capacitance of the dual-electron-injector stack. Good agreement is observed between the experimental data and this model. This model will be the starting point in designing more complicated device arrays for nonvolatile memory applications.

Abstract: A memory array is disclosed which employs a plurality of floating gate EPROM or E 2 PROM cells. Charge to program these cells is generated from charge generators, each shared by a plurality of cells. For example, one charge generator generates sufficient charge to allow selective programming of several hundred cells. The cells can be fabricated without the requirement to withstand high potentials, with less critical geometries and in some cases as two terminal devices.

Abstract: Non-volatile semiconductor matrix random access and electrically alterablerogrammable read-only memories are disclosed. Each memory cell of the matrix memory includes a photovoltaic ferroelectric element which is remanently polarized with a write signal, and which when illuminated, produces a photovoltage which causes a field effect transistor to assume one of two states. Variable impedance means, for example, at least a diode or a breakdown diode is connected in each cell for providing a low impedance when the write gate pulse is applied to the photovoltaic ferroelectric element and for providing a high impedance when the photovoltage produced by the photovoltaic ferroelectric element is applied to the field effect transistor gate. If power to the memory is lost, by illuminating the photovoltaic ferroelectric element, the field effect transistor may be caused to assume the state which it was in before loss of power.

Abstract: A loading system for a numerical controller which employs both a main processor and a sub-processor to ease the load on the main processor. The loading system transfers a control program stored in a nonvolatile memory to a RAM using a loading program which is stored in a ROM incorporated in the sub-processor, whereby the circuit arrangement is simplified and the cost of hardware is reduced. At the time of starting the numerical controller, the main processor reads out a loading program from the ROM of the sub-processor and transfers it to the RAM for storage. The loading program thus transferred is executed by the main processor, by which a control program stored in the nonvolatile memory is transferred to the RAM, completing the loading operation.

Abstract: A sensing system for a nonvolatile memory transistor array employs reference transistors which are substantially identical to the memory transistors within the array and employs means to program the threshold voltage levels of the reference transistors to a lower level than that of the memory transistors within the array such that the changes in the electrical characteristics of both the memory and the reference transistors are proportional over time, the system thereby being rendered self-tracking.

Abstract: The invention relates to field effect transistors having a non-volatile memory effect of the MIS type. According to the invention the transistor comprises, in addition to substrate (17), a source (21), a drain (22), a grid formed by a semi-insulating film (18) and an insulating layer (19), whose semi-insulating film (18) has a thickness below 100 angstroms and is formed from a semiconductive material of groups III-V having a broader forbidden band than that of the active layer (16) on which it is deposited. Useful applications of the invention include ultra-high frequency transistors for telecommunications.

Abstract: An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through in insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.

Abstract: An electrically-erasable floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROM's Erasure is accomplished with the first-level of poly-silicon which serves as an erase electrode causing field emission of electrons from the bottom of the second-level floating gate. In this new cell structure, memory can be erased bit by bit or word by word, and the stored charge in the floating gate can be checked quantitatively by applying sensing voltage to the first poly-Si gate which is also used as erase gate. New fabrication process, mechanism of bit by bit electrically erasing and design theory of the new memory cell are also described.

Abstract: PURPOSE:To improve the reliability of a semiconductor nonvolatile memory device by checking or checking/correcting stored information when the state is transited from the storage holding state to the external access enable state. CONSTITUTION:When an external current supply is interrupted, a current is supplied to a memory section 1 from a battery 7 as a backup power supply so as to prevent the volatility of stored information in the memory section 1. When the external power supply is restored, a current is supplied to other circuits from a power supply section 6 and the state becomes the electrically accessible state. The storage information in the memory section 1 is checked by the state changeover. That is, when a power supply confirming signal is given from the power supply section 6, a main control circuit 5 sets an address counter 4 to an initial value, counts up sequentially the address so as to read the storage information of the memory section 1. A parity check circuit 3 checks the content at the same time. When no error exists in the storage information, the state is transited to the externally accessible state at a point of time when the check of the content of all the memories is finished. If there exists any error, it is regarded that the storage information in the memory section 1 is destroyed and the main control circuit raises alarm information to an external device.

Abstract: The present invention relates to storage devices which utilize a floating single crystal electrode onto which elcetrons are injected to vary the capacitance of a device which includes capacitance contributions from a pair of insulator regions and that resulting from the uncharged floating single crystal electrode. The memory cell includes at least a pair of other electrodes one of which is utilized to provide two voltage levels to cause injection of electrons and provide an interrogation or read pulse. The other of the pair is utilized as a sense electrode which capacitively senses current when a read pulse is applied to the device via a control electrode. A second embodiment utilizes a pair of injector electrodes, a separate control electrode and a sense electrode in addition to the single crystal floating electrode. A memory array incorporating a device using the single crystal floating electrode is also disclosed.

Abstract: PURPOSE:To perform a storage of charging at a low voltage by a method wherein SiO2 film is made thicker than that showing a high tonnel effect in non-volatile memory element and a transluent metal having oxidized surface is applied as a floating gate. CONSTITUTION:In non-volatile memory element composed of Si base plate 1, SiO2 4, a floating gate 6, Si3N4 7 and a gate electrode 8, the SiO2 4 has a thickness of about 2,000Angstrom having a dominating Faranodeheim tunnel phenomenon, and Si3N4 7 has a thickness of about 9,000Angstrom . Mo is used in the floating gate electrode 6 and a thermo oxidation film 11 is operated as a conductor, and when a negative voltage is applied to the gate electrode 8, Mo itself provides a mirror image effect for SiO2 4, its difference in work function for SiO2 is reduced due to a degree of energy level in MoO, resulting in reducing a sheath voltage. With this arrangement, a mere oxidation of the floating gate causes the sheath voltage to be reduced, results in providing a highly practical memory element.

Abstract: PURPOSE:To initialize a volatile memory in electric power recovery without destroying the contents of a nonvolatile memory by inhibiting transmission of a parity error to a main memory device while the initialization is in process. CONSTITUTION:In data processor 8 for recovery processing of an electric power break, the output of decoder 9 controlling arithmetic circuit 10 sets flip-flop 11. This set signal is applied as a parity-error detection inhibition signal to gate 4 of main memory unit 1. Readout data from main memory cell 2 consisting of volatile and nonvolatile memories is sent to data processor 8 via parity circuit 3, but while the above-mentioned parity-error detection inhibition signal appears, an error signal is not sent to processor 8. When an error occurs, on the other hand, parity circuit 3 sets a correct parity bit and rewrites main memory cell 2. After the above-mentioned initialization, decoder 9 resets FF11 and places the processing operation in a normal state.

Abstract: PURPOSE:To detect power-off of a power source for backup when a main power source is turned on again, by writing a specific bit pattern in a nonvolatile memory to store information before power-off of the main power source. CONSTITUTION:When a switch 6 is turned on, a CPU1 is started to compare a specific bit pattern stored in an ROM 2 with contents in a determined address of an RAM3. If they do not coincide with each other, all contents of the RAM3 are made ineffective, and the specific bit pattern stored in the ROM2 is written in a determined address of the RAM3. If they coincide with each other, all contents of the RAM3 are decided effective. If a power source 5 for backup is connected normally when the switch 6 is turned off, contents of the RAM3 are held because power is supplied continuously through a diode 8.

Abstract: PROBLEM TO BE SOLVED: To provide a portable data carrier which is provided with a burglarproof means and used for storing and processing data. SOLUTION: A data carrier is provided with a microprocessor, a nonvolatile memory composed of a programmable read-only memory, and an access memory and error memory composed of electrically rewritable read-only memory type memory elements and the microprocessor is provided with a means which, when access is tried, reads out the access and error codes of the contents of the access and error memories, stores the codes in the registers A and B, respectively, of the microprocessor, and checks an enabling key. When the enabling key is proper, the means erases the content of the access memory and, at the same time, rewrites the content of the register A in the access memory as an access code after increasing the content of the register A by one unit. When the enabling key is improper, the means erases the content of the error memory and, at the same time, rewrites the content of the register B in the error memory as an error code after increasing the content of the register B by one unit.

Abstract: PURPOSE:To accurately judge the life of memory and to increase the reliability, by reading out the data and comparing it with the data to be written in, immediately after the write-in to the nonvolatile memory. CONSTITUTION:After the write-in to the nonvolatile memory 2, the storage data of the same address is read out without fail, and the agreement between this data and the data to be written in is judged at the comparator 4. If in disagreement, it is possible that the number of write-in of the memory 2 reaches a limit, then the disagreement is informed to the microcomputer being the device to be used. The computer receiving it tries the write-in operation again, and if the result of comparison again is in disagreement, it is switched to the spare area 2'. Thus, the life of nonvolatile memory can accurately be judged and switched to the spare memory, allowing to increase the reliability of memory.

Abstract: PURPOSE:To ensure an automatic and assued execution for both the initial setting to a volatile memory and the preservation of data to nonvolatile memory, by starting the reading action of the nonvolatile memory concurrently with the initial setting to the volatile memory. CONSTITUTION:Receiving the power confidence signal PC from the power supply part 11, the CPU101 starts the memory initial setting. Thus the CPU101 delivers both the write instruction W and the memory start signal MS to all addresses of the memories 102 and 103 via the control signal lines 105 and 106 each. Receiving the instruction W, the volatile memory 102 executes the writing of the correct data, i.e., the initial setting of memory by the write designation signal. On the other hand, the write inhibition signal IW is delivered to the nonvolatile memory 103, and no write designation signal is delivered although the instruction W is supplied. Then the read designation is given to execute the reading during the initial setting of memory, thus preserving the contents of the memory 103.

Abstract: PURPOSE:To readily diagnose a malfunction in a processor of each train by providing a nonvolatile memory in the processor. CONSTITUTION:When a reader 7 is not connected to a transmission line 8, a central processing unit 5 operates as a master station, receives information representing the operation or the malfunction of train equipment in each train from the processors 6 of the trains 1-3, processes the inputted information and outputs it to an indicator 4. Each processor 6 constantly receives various data, repeatedly writes them sequentially in a memory of an information processor 21 and stores them in the memory. When a malfunction is detected by the malfunction occurrence information from the unit 5 or the decision of the processor 21, sequential data are recorded in a nonvolatile memory 23 as to minimum necessary items for diagnosing the malfunction. When the reader 7 is then connected to a transmission line 8, the unit 21 does not operate, and the reader 7 reads the malfunction date of each processor 6.

Abstract: PURPOSE:To obtain the nonvolatile memory having stable characteristics by forming a diffused layer having higher density than a substrate and the same type as the substrate partly in contact with the drain of a double gate MOSFET in a channel region and reducing the breakdown voltage between the diffused layer and the drain lower than the negative resistance generating voltage of the FET in a writing mode CONSTITUTION:There are formed on the main surface of a P type Si 1 a field oxide film 3, a gate oxide film 4, a P-added polysilicon floating gate 5, a film 6 oxidized on the surface of the polysilicon 5, and a P-added polysilicon controlled gate 7 An N type source 8 and drain 9 are formed thereon, openings 10-12 are selectively perforated, and aluminum electrodes are provided therethrough A P type layer 16 is partly formed in the channel in contact with the drain 9, and the withstand junction voltage between the drain 9 and the layer 16 is set lower than the negative resistance generating voltage of the memory FET in case of writing operation mode Even if the substrate and the source are grounded and sufficiently high voltage is applied to the controlled gate and the voltage of the same polarity is applied to the drain (in writing) no negative resistance occurs and discrete excessive writing phenomenon does not occur according to this configuration

Abstract: MNOS storage sites have been integrated with an n-channel CCD to produce a nonvolatile memory capable of storing sampled analog signals. Analog signals, sampled at the CCD input, are stored as trapped charge in the MNOS dielectric and may be replicated nondestructively after four days of storage with a linear dynamic range of 33 dB.

Abstract: A field programmable semiconductor memory device comprises regular word lines (W), regular bit lines (B), regular memory cells (MC) connected at the intersections of the regular word lines (W) and the regular bit lines (B), at least one test word line (TW) adjacent one of the regular bit lines (B) and alternately arranged conducting (10d, 10f) and non-conducting (10c, 10e) test memory cells arranged at the intersections of the test bit lines (TB) and the regular word lines (W). To enable the insulation between adjacent word lines (W) to be tested, the test bit line (B) and the regular word line (W) are insulated from one another by an insulating layer (24) in each non-conducting test memory cell (10c, 10e).