Non-recurring engineering

Abstract: The growth in number of fuzzy logic applications led to the need of finding efficient ways to implement them. The advantage of using Field Programmable Gate Arrays (FPGA) is the ease with which controllers can be re-designed based on requirements without incurring major non recurring engineering (NRE) costs. In this paper, the implementation of a Mamdani Fuzzy Inference System has been demonstrated with the application of a Home Water Sprinkler System. The design of the Home Water Sprinkler System uses two inputs, Temperature and Soil Humidity, to give a single output, Watering Duration. VHDL programming language is used for creating the design in which simulations are carried out to check the functional verification of individual blocks. The design created on VHDL platform was synthesized, verified and implemented using Xilinx Integrated Software Environment (ISE) Version 6.1. The bit stream created is downloaded onto the Xilinx Virtex 2 FPGA which is mounted on a V2MB1000 board. For the verification of FIS, DIP switches and push buttons were used to simulate inputs. The outputs and inputs were displayed on the two seven segment LED displays. The accuracy of the model on FPGA was compared with simulation results obtained using MATLAB & Fuzzy Logic Tool Box. The results obtained from the two models differed with a Root Mean Square (R.M.S.) error of 0.8%.

Abstract: Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineering (NRE) costs and turn-around-time but suffer from higher power consumption and lower performance. Power reduction for structured ASICs uses extensive clock and supply power-down of unused circuitry and use of low power devices. However, due to the limited granularity of power-down, physical design (specially placement) should be performed to maximize the components that can be powered down. In this paper, we present the first placement algorithm to specifically target this problem. Our tool, PASAP (Power Aware Structured ASIC Placement), minimizes the clock and leakage power by maximizing the fraction of the structured ASIC that can be powered down or disconnected from clock tree. On a set of large benchmark designs, PASAP reduces clock and leakage power by 32% and 17% respectively compared to prior structured ASIC placement tool RegPlace [1] incurring 17% penalty in wirelength and 30% longer runtime.

Abstract: Todays Electronic Design Automation industry is greatly affected by increased Non Recurring Engineering (NRE) costs and Time-to-Market (TTM) due to the incremental and iterative steps followed in the conventional digital IC design and automation flow. Reducing NRE cost and TTM at the same time is a daunting task to the research community without compromising on the performance. However, the complexity of hierarchical design steps can be reduced drastically by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs stored in pre-computed technology libraries. We use the Dynamic Libraries, which store the layouts of the already designed blocks and their references for the later use in further designs which reduces the design time and design cost significantly. Further we have exploited the functional symmetry and negation-permutation negation (NPN) class representations to decoct the library size and number of comparisons to further improvise on design time which results in reduced TTM. The functional symmetry reduced the number of required pre-computed circuits in our experiments from 1031 to 222 (464.4% reduction in the memory size). We further validated our methodology with adders and multiplier blocks which are the basic elements of any processor or controller.

Abstract: Currently ASIC applications, such as multimedia processing, require shorter time-to-market and lower cost of Non Recurring Engineering (NRE). Also, with the IC manufacturing technology developing continually, from transistor level to logic gate level, the size of design cells in digital circuits is increasing correspondingly. New design methodology is in urgent need to meet the requirement for the developing processing technology and shorter time-to-market in IC industry. This paper proposed the concepts and principles of operator design methodology, then focused on the entropy coding application based on the operators and finally presented the implementation results. The results show that with the proposed methodology, a comparable hardware performance can be obtained against the traditional standard cell based design flow. Furthermore, the design speed can be improved efficiently.