NMOS logic

Abstract: Logic gates were fabricated from an array of configurable switches, each consisting of a monolayer of redox-active rotaxanes sandwiched between metal electrodes. The switches were read by monitoring current flow at reducing voltages. In the “closed” state, current flow was dominated by resonant tunneling through the electronic states of the molecules. The switches were irreversibly opened by applying an oxidizing voltage across the device. Several devices were configured together to produce AND and OR logic gates. The high and low current levels of those gates were separated by factors of 15 and 30, respectively, which is a significant enhancement over that expected for wired-logic gates.

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Abstract: Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU Memory is observed to be ~ 780x.

Abstract: Partial table of contents: Properties and Definitions of Digital ICS. Diodes. Bipolar Junction Transistors. Diode-Transistor Logic (DTL). Schottky Transistor-Transistor (STTL). Other TTL Gates. Basic Emitter-Coupled Logic (ECL). MECL III and ECL 10K. Other ECL Gates. Introduction to MOS Digital Circuits. Resistor Loaded NMOS Inverter. Enhancement-Depletion Loaded NMOS Inverter. NMOS Gates. CMOS Inverter. CMOS Tri-State Gates. CMOS Drivers. Dynamic CMOS. BiCMOS. Latches and Flip-Flops. Semiconductor Read-Only Memories. Direct Coupled NMESFET Logic (DCFL) Inverter. Schottky Diode NMESFET Logic (SDFL) Inverter. Other Gallium Arsenide Logic Family Inverters. Gallium Arsenide NMESFET Gates. Appendices. Supplementary Reading. Selected Answers. Index.