Abstract: Floating-point arithmetic implementation follows basic operations like addition, subtraction, multiplication and division. In scientific computation, digital signal processing rounding the number to true value leads to error in representing the original number. This paper includes a single-precision half unit biased floating-point format representation and provides the implementation technique of HUB addition and compared with standard floating-point addition. Implementation of HUB format in adding two floating-point numbers reduces the area by 20.6%, reduces the power by 16.7%. It also reduces the error due to rounding.

Abstract: BCD arithmetic is preferred in applications such as financial, scientific and commercial owing to its comparatively high precision. This paper presents an efficient decimal multiplication architecture. The architecture adopted in this work helps in reducing the partial product reduction structure height to half compared to existing digit-by-digit-based multiplication schemes. Partial product reduction is carried out using carry save adders, efficient multi-operand binary-to-decimal converters and BCD adders. The performance of the proposed decimal multiplier proves that the modifications at partial product reduction stage significantly improve their area and delay compared to the existing architecture. The same is validated by the simulation results which prove that the proposed design utilizes 2.7 times lesser area, 1.27 times faster and 3.51 times better area-delay product than the best performing existing design.