Abstract: Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the multiplication most-significant bit first and produces a conventional sign-and-magnitude product (most significant n bits) by means of an on-the-fly conversion. The resulting implementation is fast and regular and is very well suited for VLSI. The LRCF scheme for general radix r and a radix-4 signed-digit implementation are presented. >

Abstract: Bit serial multiplication schemes for hardware implementation of arithmetic in a finite field of characteristic two are considered. In addition, certain aspects of polynomial bases in finite fields are investigated.

Abstract: An electronic computer is a high speed calculating device capable of storing vast amounts of numerical information and performing elementary arithmetic operations (addition, multiplication, etc) on the various numbers contained in its storage locations. A computer program is a set of instructions, written in some language that can be ‘understood’ by a computer, that determines how the computer is to operate on the information (i.e. the numbers) fed to it.

Abstract: A neuron is modeled as a linear threshold gate, and the network architecture considered is the layered feedforward network. It is shown how common arithmetic functions such as multiplication and sorting can be efficiently computed in a shallow neural network. Some known results are improved by showing that the product of two n-bit numbers and sorting of n n-bit numbers can be computed by a polynomial-size neural network using only four and five unit delays, respectively. Moreover, the weights of each threshold element in the neural networks require O(log n)-bit (instead of n-bit) accuracy. These results can be extended to more complicated functions such as multiple products, division, rational functions, and approximation of analytic functions. >

Abstract: Summary. A definition of rational numbers and some basic properties of them. Operations of addition, substraction, multiplication are redefined for rational numbers. Functors numerator (num p) and denominator (den p) (p is rational) are defined and some properties of them are presented. Density of rational numbers is also given.

Abstract: A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic (324) removes the bias from one operand exponent before the two operand exponents are added together in adder (322) for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.

Abstract: We present algorithms for accurately converting floating-point numbers to decimal representation. The key idea is to carry along with the computation an explicit representation of the required rounding accuracy.We begin with the simpler problem of converting fixed-point fractions. A modification of the well-known algorithm for radix-conversion of fixed-point fractions by multiplication explicitly determines when to terminate the conversion process; a variable number of digits are produced. The algorithm has these properties: No information is lost; the original fraction can be recovered from the output by rounding.No “garbage digits” are produced.The output is correctly rounded.It is never necessary to propagate carries on rounding.We then derive two algorithms for free-formal output of floating-point numbers. The first simply scales the given floating-point number to an appropriate fractional range and then applies the algorithm for fractions. This is quite fast and simple to code but has inaccuracies stemming from round-off errors and oversimplification. The second algorithm guarantees mathematical accuracy by using multiple-precision integer arithmetic and handling special cases. Both algorithms produce no more digits than necessary (intuitively, the “1.3 prints as 1.2999999” problem does not occur).Finally, we modify the free-format conversion algorithm for use in fixed-format applications. Information may be lost if the fixed format provides too few digit positions, but the output is always correctly rounded. On the other hand, no “garbage digits” are ever produced, even if the fixed format specifies too many digit positions (intuitively, the “4/3 prints as 1.333333328366279602” problem does not occur).

Abstract: A general theory of noise in avalanche photodiodes (APDs), photomultipliers, and other cascaded multiplication devices in which ionization is independent of a carrier's history is presented. The theory is based on a composition law that allows the calculation of the gain distribution of a multilayer structure from the known distributions for each layer. The composition law is used to establish some well-known results and a number of new results. New formulas are derived for the gain and excess noise of a general double-carrier structure composed of multiple identical stages. A set of differential equations is derived for the case of continuous multiplication, as in a conventional APD. New results are reported for the noise of the staircase APD and for an APD with two regions of constant but different ionization ratios. The latter can be used to model the InGaAs/InP separated absorption and multiplication APD. >

Abstract: It is shown that carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a wide variety of algorithms for high-speed digital signal processing. Existing strategies for the realization of inner-product based and recursive algorithms are recalled. New approaches are presented for carry-save implementation of decision-directed algorithms such as division, modulo multiplication, and CORDIC. >

Abstract: VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit number representations are proposed. A prototype adder chip is implemented with 10- mu m CMOS technology to confirm the principle of operation. A multiplication scheme using four-input current-mode wired summations for realizing a high-speed small-size multiplier is presented. The 32*32-b multiplier is composed of 18800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2- mu m CMOS technology. It is shown that the technology is also potentially effective for the reduction of the data-bus area in VLSI. >

Abstract: This study was designed to gain information about the understandings children in Israel and the United States have about multiplication and division of whole numbers that may be useful in building accurate understandings of these operations with decimals and the extent to which they hold conceptions about these operations that may interfere with their work with decimals. Data from interviews of the fourth and fifth graders indicate that students of this age already hold misconceptions such as “multiplication always makes bigger.” However they also hold conceptions that are prerequisite to understanding the area model of multiplication and the measurement model of division. These early conceptions might be used to build understanding of multiplication and division by decimals. Implications for the content and sequencing of instructional activities are presented.

Abstract: (1990). Multiplication Modules and Ideals. Communications in Algebra: Vol. 18, No. 12, pp. 4353-4375.

Abstract: The letter describes a new algorithm for modulator multiplication using carry-save adders. The proposed algorithm is based on the sign-estimation technique. A carry-save adder structure consisting of three rows of n + 3 simple 1-bit adder cells, and two copies of 3-bit carry look-ahead logic can be used to implement a single step of the algorithm. A completely pipelined array for modular multiplication designed by cascading n carry-save adders performs modulator multiplication at the clock rate.

Abstract: A systolic architecture is presented which is capable of both input and output conversion with a throughput equal to that of the fast residue number system (RNS) processes of addition and multiplication. The converter can be used with an arbitrary RNS (within certain realization-imposed limits). An actual anticipated VLSI layout is described that will be programmable for RNSs with up to eight moduli of six bits or less. This should provide an off-the-shelf solution for many RNS conversion requirements. >

Abstract: A simple but powerful parallel architecture based on the classical associative processor model, which allows bit-parallel computation and communication, is proposed. Complex operations such as multiplication execute in O(m) cycles, as opposed to O(m/sup 2/) for bit-serial machines. This permits very fast processing of floating-point data. A bit-parallel communication network that exploits associative data location independence is presented. It provides the system with a reconfiguration capability, which improves chip yield, as well as fault tolerance. The simplicity of the architecture lends itself to VLSI implementation and hence allows the construction of a bit-parallel, word-parallel, and massively parallel (P/sup 3/) computing system. >

Abstract: A physics-based model that describes the multiplication factor and the generation current of bipolar transistors is presented. No extra fitting or model parameters are needed in the model. Comparison on the present model, the model employed in SPICE, and measurement data are included.

Abstract: Transforms such as the DCT are useful for image compression. One close relative of the DCT is preferred for its arithmetic simplicity. A method is described whereby the image compression is done with no multiplications. Other enhancements are made to improve image quality.

Abstract: We present a unified approach to the problem of characterizing the Fredholm multiplication and composition operators on the Hardy spaceH 2.

Abstract: A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

Abstract: Alternate formulations of Horner's rule which partitions the algorithm into inner-product computations are studied. Fixed-point inner products may be implemented with distributed arithmetic structures that use table-lookup in place of multiplication. Distributed arithmetic can be smaller and faster than lumped arithmetic in technologies where memory is cheaper than logic. The partitioned algorithms may be mapped to mesh-connected or tree-connected VLSI architectures. The partitions may be chosen to optimize cost measures and constraints that are functions of area, latency, period, and arithmetic precision. These structures are compared with a tree structure for polynomial evaluation. It is considered that each has advantages depending on problem size and target technology. >

Abstract: A design of a parallel multiplier is presented in which the time-consuming multiplication process is recursively decomposed into simple summation processes that can be executed simultaneously. At each recursive step, each multiplier and multiplicand is partitioned into four groups of bits and produces 16 partial product terms. An efficient summation process of adding up these partial product terms is proposed. These terms are grouped in accordance with their relative bit positions and with the use of three-to-two counters. Based on the proposed summation process, the multiplier can achieve a speed complexity of order O(log2n). Owing to its regular structure, the proposed parallel multiplier is feasible for VLSI implementation. In the paper, the designs of parallel multipliers implementing various orders of partitions are also studied. The results show that partitioning each multiplier and multiplicand into five groups of bits can generally yield a higher speed performance with less chip area for arbitrary bit size.

Abstract: An apparatus is provided for logarithmic subtraction that is suitable for general purpose computing using the sign logarithm number system. In the sign logarithm number system, a sign bit is concatenated to a fixed point approximation of the logarithm of the absolute value of the real number being represented. Multiplication and division are easy and fast because the only steps required are to add or subtract the logarithms and exclusive OR the sign bits. In the prior art, logarithmic arithmetic has been restricted to limited precision applications (8-16 bits), such as digital filtering, because of the problem of accurate, high speed subtraction. The present invention provides a new circuit for subtracting two numbers represented in logarithmic form which makes design of arithmetic units for larger word sizes (32 bits) practical. The subtraction circuit approximates log b |1-b z |, where z is the difference of the logarithms being subtracted. The value of z is shifted, and the high part of z is used as input to two ROMs. The output of the first ROM is added to the product of the second ROM and the low part of the shifted z value. In the case of z being close to zero, the low part of z is used as input to a third ROM, which provides a more accurate approximation of log b |1-b z |.

Abstract: An apparatus and method for solving a system of linear equations uses a sequence of matrix-vector multiplications wherein the matrix to be multiplied is derived from an expansion point matrix that permits rapid convergence. The matrix-vector multiplication form of the sequence permits calculations to be performed on a network of parallel processors.

Abstract: A data processing system uses the same structure and hardware to implement either a general purpose multiplier or arithmetic operations associated with the least-mean-squares (LMS) algorithm. Multiplier and adder circuits are time-shared to perform the myriad functions. In one form, further modified Booth's algorithm is utilized so that an output product of two binary input numbers may be quickly formed by executing a series of multiplications and accumulations. The operation is pipelined for continuous processing activity.

Abstract: An apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its "personality" by virtue of receiving consecutive bits of the multiplicand. The receipt of consecutive bits by each slice eliminates the need for the interconnection of successive slices in separate chips. Thus, the apparatus allows the avoidance of significant timing delays, inherent in such interchip connections, which diminish computer system multiplication performance, and allows the multiply cycle time to be as fast as a latch-to-latch transfer across chips. Each slice may include a binary multiplier for forming a product of two numbers on an iterative basis, an accumulator connected to the multiplier for adding the products from the multiplier, and a carry-out register connected to the accumulator for storing carry-out data.

Abstract: A supplementary teaching instrument based on mathematical basic theories and principles as well as child psychology. The invention employs a number of rectangular blocks of a prescribed shape which occupy a predetermined area when assembled together, and a corresponding area of triangular shaped blocks of various sizes and shapes. In addition to creating artistic designs by different arrangements of the blocks which may be of different colors, the rectangular blocks can be used in the fashion of a domino game, and the dimensional relationship between the triangular blocks and the rectangular blocks teach the basic concepts of mathematics including addition, substraction, multiplication, fractions, areas, and the like.

Abstract: An algorithm based on O/sup 2/DFT (odd-time odd-frequency discrete Fourier transform) is presented for the computation of the EDCT-2 of purely real sequences. Comparison of this algorithm with two others available in the literature shows that it is computationally superior for EDCT-2 evaluation of real sequences (N>8). Its computational advantage is based on its lesser real multiplication requirements. >