Abstract: Cryptographically secure pseudo-random number generators known so far suffer from the handicap of being inefficient; the most efficient ones can generate only one bit on each modular multiplication (n2 steps). Blum, Blum and Shub ask the open problem of outputting even two bits securely. We state a simple condition, the XOR-Condition, and show that any generator satisfying this condition can output logn bits on each multiplication. We also show that the logn least significant bits of RSA, Rabin's Scheme, and the x2 mod N generator satisfy this condition. As a corollary, we prove that all boolean predicates of these bits are secure. Furthermore, we strengthen the security of the x2 mod N generator, which being a Trapdoor Generator, has several applications, by proving it as hard as Factoring.

Abstract: The increasing need for large-scale computations has led to new interest in optical parallel computing. Digital parallel processing can be implemented using optical truth table look-up techniques. With optical-logic-based pattern recognition, a content-addressable memory can be constructed. The use of the EXCLUSIVE OR and NAND logic operations to achieve content addressability is discussed. This memory system can be used to perform digital truth table look-up processing. Operations such as addition and multiplication of 4-, 8-, 12-, and 16-bit words in parallel arrays are then directly possible. The number of reference patterns that must be stored is dramatically reduced by the use of the (binary-coded) residue number system and logical reduction tech-niques. An example 16-bit multiple-word-parallel (of order 1000) fixed-point multiplier is discussed.

Abstract: A multiple precision multiplication device includes accumulators coupled to the output of an array multiplier. The accumulators store partial products which are then added back into partial products generating during succeeding multiplication steps. The final product is output from the accumulators only after all partial products have been added in.

Abstract: The arithmetic pipeline processor (which is used for computer graphics such as a flight simulator) is a group of boards capable of solving an equation of the form A.sup.m B.sup.n +C.sup.o D.sup.P +E.sup.q F.sup.r +G.sup.s H.sup.t where A, B, C, D, E, F, G, H are 32-bit implied one floating point numbers, and m, n, o, p, q, r, s, t can take on the values 1/4, 1/2, 1, 2 and 0. It includes a digital logarithmic calculator using shifters and stored tables to perform arithmetic functions such as multiplication, division, squares, square roots, and fourth roots. It comprises two input ports each capable of receiving digital data N bits wide. Included are a log transform unit, a log sum or difference unit and an antilog unit. Following these is an M-bit Aritmetic Logic Unit (ALU) and circuitry for converting between fixed point and floating point numbers. It uses piece wise linear approximation in conjunction with stored slope information in tables to do the transform calculation of logarithms and antilogarithms. The M-bit arithmetic unit performs accumulation of up to K terms. In a specific emodiment, N=32, M=36, and K=128. Note that a pipeline processor has no central processing unit or software in itself, but it may interface with a computer for inputs and outputs including control information.

Abstract: Recent advancements in residue arithmetic have given rise to a complex number system variant which better than halves RNS multiplication complexity. This advantage is applied to the problem of implementing a high-speed radix-4 RNS FFT. It is shown that a significant improvement in both complexity and speed can be achieved.

Abstract: This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.

Abstract: A novel optical system for real-time processing of the multiple matrix product is proposed. In this system, all the N × N matrices are kept in the N2 format without any scanning scheme. This system can easily be extended to that for multiplication of more than three matrices by using a holographic unidirectional diffuser. We estimate the operational error and the power efficiency of this system to give guidelines for the design of the matrix masks and the unidirectional diffuser. The preliminary experiments of multiplication of two and three matrices are successfully demonstrated with an average error of 1.9% and 4.7%, respectively.

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Abstract: A digital signal processor (DSP) is described which achieves high processing efficiency by executing concurrently four functions in every processor cycle: instruction prefetching from a dedicated instruction memory and generation of an effective operand, access to a single-port data memory and transfer of a data word over a common data bus, arithmetic/logic-unit (ALU) operation, and multiplication. Instructions have a single format and contain an operand, index control bits, and two independent operation codes called “transfer” code and “compute” code. The first code specifies the transfer of a data word over the common data bus, e.g., from data memory to a local register. The second determines an operation of the ALU on the contents of local registers. A fast free-running multiplier operates in parallel with the ALU and delivers a product in every cycle with a pipeline delay of two cycles. The architecture allows transversal-filter operations to be performed with one multiplication and ALU operation in every cycle. This is accomplished by a novel interleaving technique called ZIP-ing. The efficiency of the processor is demonstrated by programming examples.

Abstract: A signal processing device for frequency multiplication of an analog signal by an adjustable multiplication factor. The input analog signal is digitized using a delta modulator and read into a random access memory at a first clock rate. The data is read out of the memory at second clock rate and then converted back to an analog output signal. The multiplication factor is a function of the adjustable ratio of the two clock rates.

Abstract: ?(n log n) time is required to sort n integers using comparison, addition, subtraction, multiplication, division, indirect addressing, and mildly restricted truncation.

Abstract: A new multidimensional Hartley Transform is defined and a vector-radix algorithm for fast computation of the transform is developed. The algorithm is shown to be faster (in terms of multiplication and addition count) compared to other related algorithms.

Abstract: A method is presented for measuring the difference between two low frequencies with high resolution. The method is based on multiplying the two incoming frequencies by a large factor and then using a BCD up/down counter to store and display the resulting frequency difference. To achieve a resolution of n decimal places, the multiplication factor must be 10n and the decimal point must be placed n digits to the left of the least-significant digit of the displayed results. The inherent ± 1 count error will result in a resolution of ±10-n Hz. Frequency multiplication is achieved using a phase-locked loop stage which provides a multiplication factor of 103. This method has the advantage of being simpler and less expensive compared to other methods using period-measuring techniques.

Abstract: A special technique for remediating difficulty in simple multiplication

Abstract: A teaching methodology provides the student with hand conformed symbols representative of the numbers 6 through 9 Observation of these symbols permits the students to use their mastery of multiplication of the numbers 1 through 5 and 10 to solve problems in multiplication and division involving the numbers 6 through 9

Abstract: PURPOSE: To obtain a digital signal processor DSP having high throughput by providing plural multipliers to an arithmetic part and having direct connections among those multipliers, a data memory and an arithmetic logic unit respectively. CONSTITUTION: The 1st multiplier 311 multiplies the output data on the 2st port 13a of a double-port RAM 13 by the data read out the left face of a ROM 14. While the 2nd multiplier 312 multiplies the output data on the 2nd port 13b of the RAM 13 by the data read out of the right face of the ROM 14. The results of these two multiplications carried out by the multipliers 311 and 312 are given to the 1st arithmetic logic circuit ALU321 and added with each other..The result of this addition is given to the 2nd ALU322. Then the result of multiplication of the ALU321 is added with the cumulative results of multiplication stored in an accumulator ACC33. The result of this addition is stored in the ACC33 and then delivered via a data bus 4. In such a way, the throughput is improved for a digital signal processor. COPYRIGHT: (C)1987,JPO&Japio

Abstract: Golub's method of complex multiplication is extended to other contexts such as multiplication with some 2 x 2 matrices and Latin squares. Some applications in further speeding up the FFT or other fast transforms are discussed.

Abstract: A digital acousto-optic device for performing vector-matrix multiplication The device comprises two multitransducer acousto-optic cells imaged onto each other The first cell receives the elements of the input vector in parallel The second cell receives the elements of sequential row vectors of the matrix in parallel The data in the two cells act to modulate a light beam passing therethrough The modulated light beam is detected to produce an output data stream containing the elements of the output vector The invention uses binary coded data for high accuracy (˜16-bits)

Abstract: What if we were multiplying ​one positive and one negative number​? For example, what is ​4 x (-2)?​ To understand what the answer would be, we’re going to approach this in three ways: Problem 2:​ ​What is 4 x (-2)? a. What is 4 x 0 = ____________ b. What is 2 + -2 = ___________ (Use a number line, if necessary) c. Since we know that 2 + -2 = _____, let’s replace the 0 in 4 x 0 with the following:

Abstract: A novel optical system for real-time processing of a multiple matrix product is proposed. In this system, there is no scanning mechanism, and all of the N×N matrices to be multiplied have the N2 format. This system can easily be extended to that for multiplication of more than three matrices using a holographic unidirectionally diffusing screen. The preliminary experiments of multiplying three matrices based on this system is successfully demonstrated with a mean error of 4.7%.

Abstract: Three new arrays for unsigned and signed multiplication, and for multiplication/addition are presented. It is assumed that the factors are axpressed in 2's complement, while the addend (in the latter array only) and the result are expressed in a redundant notation. The arrays operate in serial-parallel way, since one factor is input in parallel, while the second factor and the addend (in the case of multiplication/addition) are entered digit by digit starting from the most significant one; the result is also produced serially with the most significant digit first. Hence, the arithmetic unit presented is suitable to be used as basic block of special purpose processors performing functions such as non-recursive digital filtering, signal correlation and matrix multiplication. Indeed, they have the same speed improvements as other similar units using redundant representations for the result, with a cost equivalent to their counterparts based on full 2's complement representation.

Abstract: A new recursive algorithm for deriving the layout of parallel multipliers is presented. Based on this algorithm, a network for performing multiplications of two's complement numbers is proposed. The network can be implemented in a synchronous or an asynchronous way. If the factors to be multiplied have N bits, the area complexity of the network is O(N2) for practical values of N as in the case of cellular multipliers. Due to the design approach based on a recursive algorithm, a time complexity O(log N) is achieved.It is shown how the structure can he pipelined with period complexity O(1) and used for single and double precision multiplication.

Abstract: PURPOSE:To accurately control a motor with an inexpensive electric circuit by raising the resolution by multiplying the output signal of an encoder. CONSTITUTION:The title controller has a rotary encoder 10, a multiplier 20 for multiplying the output signal, a multiplication signal number discriminator 40 for discriminating what the multiplication signal is in number, a memory 50 for storing the periodic error data between the multiplication signals measured in advance in response to the signal number of the multiplication signal, an error signal generator 60 for generating the error signal by reading out the periodic error signal corresponding to the multiplication signal number from the memory, a control circuit 80 for generating a motor control signal SC corrected for the periodic error of the multiplication signal by inputting the signal, and a drive circuit 100 for driving the motor 1 by the motor control signal SC.