Abstract: Part I: Foundations for teaching mathematics: Mathematics today for elementary schools Foundations for planning effective teaching Organizing for instruction Assessment in elementary school mathematics. Part II: Four general standards: Mathematics and problem solving Communication, reasoning and connections. Part III: Procedures and materials: Early experiences with mathematics Extending understanding of numbers and numeration Teaching addition and subtraction of whole numbers Teaching multiplication and division of whole numbers Informal geometry Fractional numbers common fractions Fractional numbers Decimal fractions and percent Measurement Tables, graphs, statistics, and probability.

Abstract: This paper examines common implementations of linear algebra algorithms, such as matrix-vector multiplication, matrix-matrix multiplication and the solution of linear equations. The different versions are examined for efficiency on a computer architecture which uses vector processing and has pipelined instruction execution. By using the advanced architectural features of such machines, one can usually achieve maximum performance, and tremendous improvements in terms of execution speed can be seen over conventional computers.

Abstract: Adults' performance of simple arithmetic calculations (addition, multiplication, and numerical comparison) was examined to test predictions of digital (counting), analog, and network models. Although all of these models have been supported by studies of mental addition, each leads to a different prediction concerning relations between the times required for addition, multiplication, and numerical comparison. Pairs of single-digit integers were presented and reaction times (RTs) for adding, multiplying, and comparing the stimuli were collected. A high correlation between RT for addition and multiplication of the same digits was obtained. This result is consistent with a network model, but presents difficulties for both analog and counting models. A "ties" effect of no increase in RT with increases in problem size for doubles such as 2 + 2 has been found in previous studies of addition using verification procedures, but was not found with the production task employed in the present study. Instead, a different kind of ties effect was found. Reaction time for both addition and multiplication of ties increased more slowly with problem size than did RT for non-tie problems. This ties effect, and the finding that probability of making errors contributes independently of problem size to RT support a distinction between location and accessibility of information in a network. Language: en

Abstract: The adaptation of the Cooley-Tukey, the Pease and the Stockham FFT's to vector computers is discussed. Each of these algorithms computes the same result namely, the discrete Fourier transform. They differ only in the way that intermediate computations are stored. Yet it is this difference that makes one or the other more appropriate depending on the application. This difference also influences the computational efficiency on a vector computer and motivates the development of methods to improve efficiency. Each of the FFT's is defined rigorously by a short expository FORTRAN program which provides the basis for discussions about vectorization. Several methods for lengthening vectors are discussed, including the case of multiple and multi-dimensional transforms where M sequences of length N can be transformed as a single sequence of length MN using a 'truncated' FFT. The implementation of an in place FFT on a computer with memory-to-memory architecture is made possible by in place matrix-vector multiplication.

Abstract: 1. An Introduction to Problem Solving 1-1 Mathematics and Problem Solving 1-2 Explorations with Patterns 1-3 Reasoning and Logic: An Introduction 2. Numeration Systems and Sets 2-1 Numeration Systems 2-2 Describing Sets 2-3 Other Set Operations and Their Properties 3. Whole Numbers and Their Operations 3-1 Addition and Subtraction of Whole Numbers 3-2 Algorithms for Whole-Number Addition and Subtraction 3-3 Multiplication and Division of Whole Numbers 3-4 Algorithms for Whole-Number Multiplication and Division 3-5 Mental Mathematics and Estimation for Whole-Number Operations 4. Algebraic Thinking 4-1 Variables 4-2 Equations 4-3 Functions 5. Integers and Number Theory 5-1 Integers and the Operations of Addition and Subtraction 5-2 Multiplication and Division of Integers 5-3 Divisibility 5-4 Prime and Composite Numbers 5-5 Greatest Common Divisor and Least Common Multiple 5-6 *Clock and Modular Arithmetic 6. Rational Numbers as Fractions 6-1 The Set of Rational Numbers 6-2 Addition and Subtraction of Rational Numbers 6-3 Multiplication and Division of Rational Numbers 7. Decimals and Real Numbers 7-1 Introduction to Decimals 7-2 Operations on Decimals 7-3 Nonterminating Decimals 7-4 Real Numbers 7-5 Using Real Numbers in Equations 8. Proportional Reasoning, Percents and Applications 8-1 Ratios, Proportions and Proportional Reasoning 8-2 Percents 8-3 Computing Interest 9. Probability 9-1 How Probabilities are Determined 9-2 Multistage Experiments with Tree Diagrams and Geometric Probabilities 9-3 Using Simulations in Probability 9-4 Odds, Conditional Probability, and Expected Value 9-5 Using Permutations and Combinations in Probability 10. Data Analysis/Statistics: An Introduction 10-1 Displaying Data: Part I 10-2 Displaying Data: Part II 10-3 Measures of Central Tendency and Variation 10-4 Designing Experiments/Collecting Data 10-5 Abuses of Statistics 11. Introductory Geometry 11-1 Basic Notions 11-2 Polygons 11-3 More about Angles 11-4 Geometry in Three Dimensions 11-5 *Networks 12. Constructions, Congruence, and Similarity 12-1 Congruence through Constructions 12-2 Other Congruence Properties 12-3 Other Constructions 12-4 Similar Triangles and Similar Figures 12-5 *Trigonometry Ratios via Similarity 12-6 Lines and Linear Equations in a Cartesian Coordinate System 13. Concepts of Measurement 13-1 Linear Measure 13-2 Areas of Polygons and Circles 13-3 The Pythagorean Theorem, Distance Formula, and Equation of a Circle 13-4 Surface Areas 13-5 Volume, Mass, and Temperature 14. Motion Geometry and Tessellations 14-1 Translations and Rotations 14-2 Reflections and Glide Reflections 14-3 Size Transformations 14-4 Symmetries 14-5 Tessellations of the Plane The Appendices are now full chapters to help students with specific technology tools: Using a Spreadsheet, Graphing Calculators, and Using a Geometry Drawing Utility. These chapters are available in the Technology Manual, which can be shrink-wrapped at no additional cost with the new textbook. See 'Packages' tab for ordering information. Answers to All/Selected Exercises Index Photo Acknowledgments *Optional Sections

Abstract: 12-and 13-year-olds were tested with two types of tasks to test their understanding of applications of the multiplication and division of positive numbers: (i) writing down calculations required to solve verbal problems, and (ii) making up stories to fit given calculations. Selected pupils were interviewed to investigate further the thinking processes involved. The results indicate (a) the pervasive nature of certain numerical misconceptions, (b) the effects of structural differences among the items; particularly whether multiplication can be conceived as repeated addition or not, and whether division has the structure of partition, quotition or rate, (c) specific effects of context attributable to such aspects as relative familiarity, and (d) various interactions between these three sets of factors.

Abstract: The improved electrooptic signal processing relies upon matrix-matrix multiplication using twos complement arithmetic. A source of pulse collimated light illuminates two two-dimension spatial light modulators that operate in a reflective mode through a polarizing beamsplitter. Each of the spatial light modulators has a matrix of optically encoded information of numbers in the twos complement binary representation so that a mixed binary representation of signals is generated within the two-dimensioned photodetector array. The mixed binary representation signals are decoded to a twos complement binary representation or a decimal representation to be useful for more conventional processing techniques. The twos complement arithmetic when incorporated with the electrooptic architecture provides for a convenient means for handling bipolar numbers, avoids the need for matrix partitioning when the matrices are real and offers a means to improve accuracy over conventional optical analog techniques.

Abstract: Matrix and vector multiplications are widely used in signal processing in operations such as FIR and IIR filtering, feature extraction and classification. Frequently, signal processing must be done in real time requiring the use of special purpose VLSI hardware. Regular structures such as systolic arrays are well suited for matrix and vector operations and are also amenable to VLSI implementation. This paper describes efficient systolic arrays for matrix and vector multiplication, at both word and bit levels, and outlines three applications relevant for signal processing: a convolver, an IIR filter and a linear classifier.

Abstract: A 32-bit CMOS floating-point multiplier is described. The chip can perform 32-bit floating-point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed-point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively; the typical power dissipation is 195 mW at 10,000,000 operations per second. High-speed multiplication techniques, a modified Booth's algorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2-/spl mu/m n-well CMOS technology; it contains about 23000 transistors 5.75/spl times/5.67 mm/SUP 2/ in size.

Abstract: This paper is concerned with the performance of linear discrete-time systems, controlled by a finite word length computer with floating-point arithmetic, and of which the state is directly measurable with an A/D converter of the same word length. The effect of using finite word length is twofold. First, roundings are made after addition or multiplication of two rounded numbers. Second, the control parameters are represented in the controller's memory, by rounded numbers. The first effect can be accounted for by considering the control parameters stochastic. The second effect is deterministic. After a description of the stochastlcs of the roundoff errors has been derived, the influence of both effects on the optimality and stability of digital control systems in the steady state in relation to a quadratic cost function is considered.

Abstract: The concept of a "Quadratic-Like" Complex Residue Number System is introduced in which certain purely imaginary numbers exist as reals within the system. It is shown that the desirable properties of a Quadratic Complex Residue Number System with regard to extremely simplified addition, subtraction, and multiplication carry over to Quadratic-Like systems. Furthermore, unlike Quadratic systems, there are no restrictions on the moduli for Quadratic-Like systems. Applications of both Quadratic and Quadratic-Like systems to real-time signal processing for ultrasonic nondestructive testing and evaluation are briefly discussed.

Abstract: An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Abstract: A hybrid arithmetic processor which combines attributes of conventional floating point (F.P) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

Abstract: Cryptographically secure pseudo-random number generators known so far suffer from the handicap of being inefficient; the most efficient ones can generate only one bit on each modular multiplication (n 2 steps). Blum, Blum and Shub ask the open problem of outputting even two bits securely. We state a simple condition, the XOR-Condition, and show that any generator satisfying this condition can output logn bits on each multiplication. We also show that the logn least significant bits of RSA, Rabin’s Scheme, and the x 2 mod N generator satisfy this condition. As a corollary, we prove that all boolean predicates of these bits are secure. Furthermore, we strengthen the security of the x 2 mod N generator, which being a Trapdoor Generator, has several applications, by proving it as hard as Factoring.

Abstract: A method of optical matrix-matrix multiplication is presented The feasibility of the method is also experimentally demonstrated by the use of a dichromated-gelatin multifocus holographic lens (hololens) With the specific values of matrices chosen, the average percentage error between the theoretical and experimental data of the elements of the output matrix of the multiplication of some specific pairs of 3 x 3 matrices is 04 percent, which corresponds to an 8-bit accuracy

Abstract: We describe a microcomputer-based system for diagnosing children's multiplication errors. The system incorporates the knowledge base of all known systematic errors which children make. In order to cope with the complexity of designing this computer-assisted learning package, we use a modular approach. Chaining the modules allows us to fit the overall system on microcomputers with limited memory capacity available at schools.

Abstract: First we give a decomposition of an FFT of length 2n into a number of one-dimensional polynomial products. If these products are computed with minimum multiplication algorithms, we show that the 2n FFT can be computed with less than 2n+1 nontrivial complex multiplications. A variation of this algorithm is also shown to give the same multiplication count as the `split-radix´ FFT.

Abstract: In this note, we introduce a novel way of doing complex arithmetic that does not involve separating the complex numbers into their real and imaginary parts. This method uses the representation of complex numbers in positional notation using a complex base - n + i, for a positive integer n, with natural numbers as digits. Addition, subtraction and multiplication can be performed directly in this positional notation and is similar to real decimal arithmetic; the main difference is in the carry digits. However, division is more complicated and the construction of a good algorithm for long division is a challenging unsolved problem. We say that an integer z (real or complex) is represented in the base b with digits from the set 6D

Abstract: Cryptographically secure pseudo-random number generators known so far suffer from the handicap of being inefficient; the most efficient ones can generate only one bit on each modular multiplication (n 2 steps). Blum, Blum and Shub ask the open problem of outputting even two bits securely. We state a simple condition, the XOR-Condition, and show that any generator satisfying this condition can output logn bits on each multiplication. We also show that the logn least significant bits of RSA, Rabin’s Scheme, and the x 2 mod N generator satisfy this condition. As a corollary, we prove that all boolean predicates of these bits are secure. Furthermore, we strengthen the security of the x 2 mod N generator, which being a Trapdoor Generator, has several applications, by proving it as hard as Factoring.

Abstract: An educational game system wherein a random selector of mathematical problems is used in playing various popular board games, simultaneously providing drill in the multiplication tables. Players must determine missing answer numbers which then dictate game piece movements. Appropriately formulated problem sets, together with dice doubles indicia, permit the random selector device to substitute for dice, spinners, and other random selection means normally used in these games. Changeable problem sets provide drill in particular multiplication tables. Usage procedure facilitates table memorization. The problems each have a missing number in which the majority are not full two digit numbers but the first or second digit of the product or one of the factors. The average value of the missing numbers for a set being less than ten. Five embodiments are disclosed, employing different random selection devices.

Abstract: Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size. Multiplication of two n x n matrices requires O(n) processors and has a time complexity of O(n2) cydes.

Abstract: In recent years one and two dimensional systolic arrays have been designed to implement a wide range of matrix operations and signal processing algorithms. This paper proposes a three dimensional systolic array architecture of N3processors to further extend the performance advantages which can be achieved through regular local data transfer. The three dimensional array is discussed in the context of fixed point matrix-matrix multiplication which requires O(N3) multiplications and additions. The array pipelines N of these problems to attain a throughput rate which is practically independent of N. The performance, size, and fault tolerance of the array are discussed for the case N=32.

Abstract: Recently, multiplication-free digital filters have been proposed for different applications to digital radio systems and signal processing. The absence of multiplication is obtained by constraining each coefficient to be sum of powers of two. In this way, multipliers are substituted by shift registers and, if appropriate, some adders. The optimal power-of-two coefficients must be computed through a nonlinear optimization procedure. Until now the problem of adapting the power-of-two coefficients of base band transversal equalizers in the case of time-varying channels had not been considered. In this paper two algorithms are proposed to cope with this problem and are compared from the viewpoint of complexity, accuracy, and convergence speed. As an application example, transmission of a biphase PSK digital radio system over a multipath fading channel is considered.

Abstract: A digital lattice filter includes a Y-adder (44) and a B-adder (106). The Y-adder (44) calculates the Y-values for a linear predictive coding voice compression technique and the B-adder (106) calculates the B-values. Each of the calculated B-values output by the B-adder (106) is input to a B-stack (118) for storage therein. The B-stack (118) delays the B-values for one sample period. Multiplier constants are contained in a K-stack (90) for output to both adders (44) and (106) for use in the multiplication operation. The final value is stored in a Y1-register (104). Each of the adders (44) and (106) are multiplexed to perform a multiplication operation followed by an addition operation to generate the respective Y- and B-values. A generated Y-value is stored in a Y-register (56) for use in the next sequential Y calculation. In addition, the generated Y-value is used as a multiplicand for generation of a B-value. Therefore, it is only necessary to store the Y-values for one clock cycle and the B-values for up to nine clock cycles, thus reducing the amount of storage space necessary. In addition, the use of two multiplexed adders reduces the required processing speed at each of the adders.