Abstract: Elements of the finite field GF(2 m ) are represented by a vector of m binary digits in such a way that multiplication can be performed by using the same logic function to compute each binary component of the product of two elements, squaring can be performed by logic circuitry that rotates the vector representing the element to be squared, and addition can be performed by logic circuitry that forms the modulo-two sum of the corresponding components of the two vectors representing the elements to be summed.

Abstract: The number of essential multiplications required to multiply matrices of size $N \times N$ and $N \times N^{0.172} $ is bounded by $CN^2 \log ^2 N$.

Abstract: A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words of BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

Abstract: In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.

Abstract: This paper introduces a simple algebra for the validation of communication protocols in message passing systems. The behavior of each process participating in a communication is first modeled in a finite state machine. The symbol sequences that can be accepted by these machines are then expressed in "protocol expressions," which are defined as regular expressions extended with two new operators: division and multiplication. The interactions of the machines can be analyzed by combining protocol expressions via multiplication and algebraically manipulating the terms.

Abstract: An associative processor is described wherein an array of associative processing cells is configured to achieve variable length multiplication of numbers, such as binary two's complement numbers, under mask control. A configuration suitable for signal multiplication is described wherein the processing sequences in all cells are compatable, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure is described, including an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.

Abstract: A new improvement of author's techniques of trilinear aggregating, uniting and canceling, is presented and applied to accelerate multiplication of matrices of moderate sizes. This results in the Exact Computing algorithms for n × n matrix multiplication in only ( n +2)[1.75( n +2)+( n 2 + 4 n +3)/3] essential multiplication steps for arbitrary even n . Also the new techniques allow us to simplify the design of the fastest known APA-algorithms for matrix multiplication.

Abstract: Recently (see [2]), we introduced the notion of decomposability for arbitrary (not necessarily finite) systems of commuting bounded linear operators on a Banach space and extended several results of I Colojoara, C Foias, St Frunza and the author to this general situation We now apply this theory to multiplication operators on Banach algebras and study multipliers on Lp (G), 1≤p<∞ for locally compact abelian groups G

Abstract: This study presents the hlerarchy of strategies used by children in solying multiplication and division problems, as they acquire the concept of linear function, It is based on an analysis of the different classes of problems, of the specific tasks given to the child and of the strategies they actually used in their solutions. Initially these strategies respect certain properties of the linear function but they ignore proportionality. Proportionality is gradually taken into account as children recognize and are able to operate with the concept of a constant coefficient.

Abstract: A series of mathematical teaching cards consisting of a plurality of decks each having a level of difficulty identification, a plurality of sets of mathematical statements having the same answer, and a deck identification number is disclosed and described. The teaching cards may be used for multiplication, division, subtraction, and addition or any combination thereof.

Abstract: With the advent of VLSI technology, it is possible to provide extremely high but inexpensive computational capability with a system consisting of a large number of identical processors organised in a simple, regular structure. In order to exploit the high computational capability of the arrays, however, it is important to employ an efficient parallel algorithm. In this paper a measure is proposed which can calculate the efficiency of an algorithm performed in a processor array. This measure is used to compare several proposed array architectures for a variety of algorithms. Finally, efficient parallel algorithms for recursive filtering problems, matrix-vector multiplication, and matrix multiplication are also proposed. 7 references.

Abstract: These algorithms are probabilistic in the following sense. The time of computation depends on random choices, but the validity of the result does not depend on them. So, worst case complexity, being infinite, is meaningless and we compute average complexity. It appears that our and Cantor-Zassenhaus algorithms have the same asymptotic complexity and they are the best algorithms actually known ; with elementary multiplication and GCD computation, CantorZassenhaus algorithm is always better than ours ; with fast multiplication and GCD, it seems that ours is better, but this fact is not yet proveen.

Abstract: Parallel algorithms using systolic and wavefront processors have been proposed for a number of matrix operations important for signal processing; namely, matrix-vector multiplication, matrix multiplication/addition, linear equation solution, least squares solution via orthogonal triangular factorization, and singular value decomposition. In principle, such systolic and wavefront processors should greatly facilitate the application of VLSI/VHSIC technology to real-time signal processing by providing modular parallelism and regularity of design while requiring only local interconnects and simple timing. In order to validate proposed architectures and algorithms, a two-dimensional systolic array testbed has been designed and fabricated. The array has programmable processing elements, is dynamically reconfigurable, and will perform 16-bit and 32-bit integer and 32-bit floating point computations. The array will be used to test and evaluate algorithms and data paths for future implementation in VLSI/VHSIC technology. This paper gives a brief system overview, a description of the array hardware, and an explanation of control and data paths in the array. The software system and a matrix multiplication operation are also presented.

Abstract: This report deals with a preliminary investigation into human error rates incurred in three relatively simple structural design tasks. The tasks were (i) table look up, (ii) multiplication of two or three numbers on an electronic pocket calculator, and (iii) ranking exercise. Error rates and frequency distributions for the three tasks are reported (a).

Abstract: Some attributes of a new method of defining the convolution and multiplication of generalised functions, too singular to be encompassed by earlier theories, are developed and its extension to the case of several variables is described.

Abstract: IΣo denotes the subtheory of first–order Peano arithmetic obtained by restricting the induction schema to formulae with only bounded quantifiers. Let EXP denote the corresponding theory obtained by adding to the language a function symbol to denote exponentiation. Let PT denote the naturally axiomatized theory (“Peano with top”) corresponding to the structures (n,+,.) for n a natural number. We show that the restriction to addition of a non-standard model of IΣo or of PT and the restriction to multiplication of a segment of a model of EXP closed under xlog x are both recursively saturated. Certain other results concerning PT are included in section III.

Abstract: A proposal is described for embedding FP and a part of FFP into a system C(IN)V of Combinatory Logic generated by the 6-tuple of combinators (A,B,C*,O,L,D) under the operation of application. At the same time C(IN)V is viewed as an algebraic extension of elementary arithmetic, including addition multiplication and exponentiation, leading to a non commutative semi-ring with an infinity of zero (infinite)-like elements. Two interesting submonoids have been selected: Lo able to represent the set of FP-Sequences and L+ able to represent the set of FP-Constructions. All basic objects forming operators like Composition, Apply To All Condition and Insert Right are then efficiently expressed inside C(IN)V. The same is done for some operators belonging to FFP as Lifting and the APPLY of LISP establishing a basis for a future reduction (operational) semantics of FP.

Abstract: PURPOSE:To make a calculation easy, to easily decode even in case when a distance between codes is >=4, and to easily change to hardware, by providing 2 specific ROMs, executing a specific conversion by each of them, and after that, executing the multiplication and addition CONSTITUTION:In a Reed-Solomon code defined on a Galois body GF(2 ), a k- dimensional vector on a Galois body GF(2) is made an address, and on its address position, the first ROM which has stored numerical information on the GF (2 ) corresponding to this k-dimentional vector is provided Also, the numerical information on the GF(2 ) is made an adress, and on its address podition, the second ROM which has stored the k-dimensional vector information on the GF(2) corresponding to the number on said GF(2 ) is provided By use of a decoding circuit as shown in the fugure, the k-dimensional vector is converted to the number on the GF(2 ) by the first ROM, and after that, multiplication is executed on the GF(2 ), the number on the GF(2 ) is converted to the k-dimensional vector by the second ROM, and after that, additon is executed on the GR(2)

Abstract: PURPOSE:To perform the frequency multiplication with good accuracy, by factorizing the value of N into the product of common multiples and obtaining the frequency multiplied by the common multiples, in obtaining the frequency N times the reference frequncy with a phase locked loop CONSTITUTION:A multiplication circuit 5 consists of a phase difference detector 7, an LPF8, a voltage controlled oscillator 9, and a 1/N1 counter 10, and a multiplication circuit 6 consists of a phase difference detector 11, an LPF12, a voltage controlled oscillator 13, and a 1/N2 counter 14 The circuits 5 and 6 are connected in cascade The circuits are factorized into plural phase locked loops PLLs as N=N1, N2-Nn, allowing to decrease the rate of multiplication of each PLL and to widen the permissible fluctuation width The PLLs having wider permissible band are used and connected in cascade to obtain N times multiplication frequency and to widen the permissible band of the reference frequency

Abstract: Let H2 (₵k) = H2 ⊗ ₵k be the usual vector-valued Hardy space and let S be the shift operator of multiplication by eit on H2 (₵k).

Abstract: A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits represented in terms of the two's complement, an exclusive-OR circuit for producing the exclusive-OR of the sign bits XS and YS of the respective values X and Y, and a selecting circuit for generating a sign bit "0" when the most significant bit of the multiplication output data from the multiplying unit is "0" and generating as a sign bit an output bit of the exclusive-OR circuit when the most significant bit is "1".

Abstract: PURPOSE:To obtain a single-precision data multiplication result speedily with high precision eventually as the multiplication result of double-precision data, by arraying addition results and multiplication results in double-precision data format CONSTITUTION:Multiplication data is inputted to a multiplier 10 by a 32-bit multiplier left input signal bus 14 and a 32-bit multiplier left input signal bus 15 The 32 upper bits of the multiplication result is outputted to an adder left input signal bus 12 and a register file through buses 16, 21, and 18, and the 32 lower bits, on the other hand, are outputted to an adder 11 through a signal line 22 as the 32 left input bits Input to the adder 11 performed through buses 12 and 13 The 32 upper bits of the addition result are sent out to the register file and an adder left input signal bus 13 through the bus 16 and signal lines 17 and 20, and the 32 lower bits are inputted as a left input directly to the adder 11 through a signal line 19

Abstract: PURPOSE:To execute an operation of multiplication and division, which is low in power consumption and high in speed, by constituting a unit circuit of a C-MOS gate, constituting a division carrying circuit of an E/D type MOS gate, and reducing the number of elements and a chip area. CONSTITUTION:Binary numbers P0, P1-P7 of 8 bits are multiplied by binary numbers B0, B1-B7 of same 8 bits, binary numbers S0, S1-S15 of 16 bits, being said multiplied value are derived, or binary numbers A0, A1-A14 of 15 bits are divided by binary numbers B0, B1-B7 of 8 bits, and the quotient shown by binary numbers Q0, Q1-Q7 of 8 bits, being said divided result, and the remainder shown by binary numbers S0, S1-S15 of 16 bits are derived. These operations are selectively designated by a control signal. In this way, when a unit circuit is constituted of a CMOS gate, and a division carrying circuit is constituted of an E/D type MOS gate, a chip area is reduced, and the processing of multiplication and division, which is low in power consuption and high in speed is executed.

Abstract: Hybrid circuits containing integrated optical detectors, waveguides, and electro-optic-switches can be used to perform a variety of digital logic operations. In combining the hybrid circuits with the carry-free residue arithmetic algorithm, different modules are designed to perform basic arithmetic operations, encoding, decoding, and scaling. Based on pipelining and parallel concepts, a vector-vector multiplier is designed to yield very high throughput rate for application involving traditionally slow computation such as matrix-vector multiplication and polynomial evaluation.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.