Abstract: In this paper we will explore the limitations imposed by entropic constraints, both in generality and for specific problems. We list below the main questions that we will address. (1) In the binary number system, addition is easy while multiplication is hard for VLSI. Is there an “ideal” number representation, in which all arithmetic operations have efficient VLSI implementations? (2) Can one build multipliers for binary numbers, which achieve both small area and fast average computation time? (3) Thompson's technique applies only to multiple output functions. How can one prove area-time bounds for single output functions? (4) What other ways are there for deriving entropic constraints from consideration of data movement? Answers to these questions will be discussed in the ensuing sections.

Abstract: Using complex numbers of the form a + b μ (where μ is a complex cube root of unity), a radix-6 FFT algorithm in which the component six-point DFT's do not require any multiplication is developed. This number system was used by Dubois and Venetsanopoulos to implement radix-3 FFT. The number of arithmetic operations for the new algorithm is compared with those of standard radix-6, radix-2, and radix-4 FFT algorithms.

Abstract: Recent advances in the way that adults perform computation in our society require reconsideration of the assumptions underlying current elementary mathematics instruction. The widespread use of calculators and computers for situations requiring precise calculation removes much of the motivation for teaching the current addition, subtraction, multiplication, and division algorithms. Yet precisely this use of computing technology now puts a premium on the exercise of estimation techniques for verifying the reasonableness of computations. These techniques, especially those that can be used “mentally” (without the use of any external tools), have been used informally for years, but never formalized for instruction. This paper discusses a range of estimation techniques, and presents in detail a series of mental estimation procedures based on the concepts of measurement and real numbers rather than on counting and integers. A set of techniques for teaching these procedures is described. These estimation techniques are evaluated against the multiple functions that elementary mathematics instruction needs to serve.

Abstract: For effective application of on-line arithmetic to practical numerical problems, floating-point algorithms for on-line addition/subtraction and multiplication have been implemented by introducing the notion of quasi-normalization. Those proposed are normalized fixed-precision FLPOL (floating-point on-line) algorithms.

Abstract: Algorithms for matrix vector multiplication are implemented using acousto-optic cells for multiplication and input data transfer and using charge coupled devices detector arrays for accumulation and output of the results. No two dimensional matrix mask is required; matrix changes are implemented electronically. A system for multiplying a 50 component nonnegative real vector by a 50 by 50 nonnegative real matrix is described. Modifications for bipolar real and complex valued processing are possible, as are extensions to matrix-matrix multiplication and multiplication of a vector by multiple matrices.

Abstract: A gate level design of a digit-slice on-line arithmetic unit is presented. This unit is designed as a set of basic modules, Processing Elements (PE), each of which operates on a single digit of the operands and the results. It is capable of executing four basic operations of addition/subtraction, multiplication and division in an on-line manner. The results are generated during the digit-serial input of the operands, beginning always with the most significant digit. A general (with respect to radix) analysis of the cost and speed of the proposed unit is also given.

Abstract: A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate array assembly generally multiplying successive eight bit bytes of the multiplier two bits at a time in each of four ranks to the full width multiplicand and producing a partial sum and carry at the end of each cycle. Each partial sum and carry then being fedback, aligned and added into the partial sum and carry produced during the multiplication of the next successive multiplier byte, until the multiplication is complete and at which time the final partial carry is converted and added to the final partial product to produce the final product.

Abstract: There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic cells. Eight stage arithmetic cell groups are set in the obliquely shifted arrangement and a ninth arithmetic cell group is provided corresponding to the shifts of their arithmetic cell groups in the array. A partial carry circuit is connected to the respective arithmetic cell groups. The arithmetic cells are all comprised of complementary MOS gates and the carry circuit is comprised of enhancement/depletion type MOS gates.

Abstract: There is shown and described a floating point processor having improved architecture and configuration. The floating point processor (FPP) performs addition, subtraction, multiplication, division and square root operations. Usually, the square root operation is not built into the FPP hardware because of the increased complexity of the design, and, therefore, cost of the goods. Rather, the square root operation is usually implemented by firmware or software. The device of this invention performs the floating point square root operation in hardware rather than in software or firmware while adding very little additional hardware to existing circuitry which is required for the basic addition, subtraction, multiplication and division operations. In addition, the operations are performed as rapidly as, or more rapidly than, prior art devices.

Abstract: New and interesting multipliers are proposed to use for the direct-multiplication of delta-modulated signals by constants. In addition to a non-recursive form, three recursive-form delta multipliers are given. The recursive multipliers are suitable for multiplication by periodic numbers or by non-periodic numbers which can be approached by periodic ones. A significantly smaller number of delta adders is needed for the realization of recursive delta multipliers, than for the non-recursive ones. In addition, an interconnecting method is suggested, if the outputs of the multipliers are to be added. With the method a significant reduction of the scaling-down is achieved as well as a reduction of the total number of the necessary adders for the realization of the multipliers. The combination of interconnecting multipliers and delta doubters gives very good results for the realization of digital filters.

Abstract: This paper describes a kind of algorithms for fast extracting square roots and cube roots, their mathematical proofs, their revised algorithm formulae, and hardware implementation of the square root algorithm. These algorithms may be of no significance for large scale computer with fast division. But I am sure that it is effective and economical to apply these algorithms to the circuit designs of some mini- and microcomputers with general multiplication and division, such as nonrestoring division.

Abstract: A floating-point arithmetic unit (FPAU), based on the residue number system, is reported which can perform addition, subtraction and multiplication. As a result, several classic problems associated with RNS based digital filters such as: overflow detection, sign detection and non-integer filter coefficients are overcome by virtue of thefloating-point representation of rational numbers over a large dynamic range. The FPAU has potential applications in computing, digital filtering, and implementing high speed, high precision Fast Fourier Transform (FFT) and Winograd Fourier Transform (WFTA). It will be shown that by using parallel small word-length architectures (viz. microprocessors), a high speed FPAU can be realized.

Abstract: Multiplication of weights by spectral radiance factors and summation is the usual method of calculating tristimulus values. The spectral-radiance-factor data may vary in abridgement (omission of intermediate data), truncation (omission of data at the extremes of the visual range), and in the case of fluorescent-lamp illuminants, omission of mercury-line data. This article sets forth recommendations for the calculation of weights for any set of spectral-radiance-factor data.

Abstract: This paper describes the use of powerful algebraic matching techniques for applying rewrite rules in equation solving. A matcher is presented that knows about the commutativlty and associativity of addition and multiplication, will provide defaults for missing summands and factors, and if necessary will solve algebraically for the value of pattern variables.

Abstract: Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.

Abstract: In a reference book for distributions [1], it is shown that the multiplication (u,f)↦uf on C∞×𝒟′, as well as on 𝒪M×𝒮′, is hypocontinuous. We show here that in both cases it is discontinuous.

Abstract: PURPOSE:To properly process each picture signal by making it have appropriate amplifying characteristics according to the types of test material and of signal sensing route. CONSTITUTION:The input signal is recorded in one input termination of image amplifying circuit 2 via the delay circuit 1. The amplifying degree of the image amplifying circuit 2 is defined by the amplifying control circuit 3. The output signal from the central control circuit 4 which has a memory function is used as the control signal for amplifying control circuit 3. Both the output of the A-D converting circuit 5, which converts an input image signal into an address signal corresponding to its signal level value, and the output of the mode selecting circuit 6, which generates a signal for selecting amplifying characteristics, are added. In the memorizing means, a multiplication degree control signal is memorized in every address which is assigned by two input signals.

Abstract: It is shown that the set of all theorems of Peano Arithmetic which mention only multiplication is a complete theory in the corresponding restricted language. The notion of a complete decidable covering of a theory is introduced.

Abstract: The efficiency of evaluation is investigated on two "big-float" systems, our LISP-interpreter-based system and Brent's FORTRAN-compiler-based system. The test problems are computations of constants e and pi, and functions sqrt(x) and exp(x). We found that speeds of big-float addition, subtraction and multiplication on our LISP-based system are nearly the same as or rather faster than those on the FORTRAN-based system. This high efficiency of basic arithmetic operations in our system is essentially due to the efficient big-integer routines in a host LISP-system written in an assembly language. Evaluation speeds of the test problems themselves on the LISP-based system are, on an average, 1.5 times slower than those on the FORTRAN-based system. The ratio of the evaluation speeds depends, however, very much on how the routines of test problems are programmed. Therefore, we conclude that the speed of a LISP-based big-float system can be reduced to within two times of that of a FORTRAN-based system.