Abstract: Among the most remarkable algorithms in algebra are Strassen's algorithm for the multiplication of matrices and the Fast Fourier Transform method for the convolution of vectors. For both of these problems the definition suggests an obvious algorithm that uses just the monotone operations + and ×. Schnorr [18] has shown that these algorithms, which use t(n3) and T(n2) operations respectively, are essentially optimal among algorithms that use only these monotone operations. By using subtraction as an additional operation and exploiting cancellations of computed terms in a very intricate way Strassen showed that a faster algorithm requiring only O(n2.81) operations is possible. The FFT method for convolution achieves O(nlog n) complexity in a similar fashion. The question arises as to whether we can expect even greater gains in computational efficiency by such judicious use of cancellations. In this paper we give a positive answer to this, by exhibiting a problem for which an exponential speedup can be attained using {+,−,×} rather than just {+,×} as operations. The problem in question is the multivariate polynomial associated with perfect matchings in planar graphs. For this a fast algorithm is implicit in the Pfaffian technique of Fisher and Kasteleyn [6,8]. The main result we provide here is the exponential lower bound in the monotone case.

Abstract: Configurations of Boolean elements for implementing a sequential GF(2n) Galois multiplication gate are disclosed. Each configuration includes a single subfield GF(2m) Galois multiplication gate, where m is a positive integral divisor of n, e.g., n=8 and m=2, and assorted controls. Also disclosed is a sequential implementation of a GF(2n) Galois linear module as described in the J. T. Ellison Pat. No. 3,805,037 wherein the controls of the sequential GF(2n) multiply gate cause the Galois addition (bit-wise Exclusive-OR) of an n-bit binary vector, Z, to the final Galois product.

Abstract: An extension of a result by Grigoryev is used to derive a lower bound on the space-time product required for integer multiplication when realized by straight-line algorithms If S is the number of temporary storage locations used by a straight-line algorithm on a random-access machine and T is the number of computation steps, then we show that (S+1)T ⩾ Ω(n2) for binary integer multiplication when the basis for the straight-line algorithm is a set of Boolean functions

Abstract: An improved organization for a FFT analyzer (or periodic function analyzer) having a reduced computing complexity. A modified organization comprises a simplified butterfly arithmetic unit in which the usual two coefficient registers or memories are required. By utilizing the registers as sources of a respective sum of and difference between sets of phase-shifted cosine values, the mechanization of the complex multiplier for such arithmetic butterfly unit in microcircuit or "chip" form may be further simplified to two controllable accumlators controlled by an exclusive-NOR gate logic system responsive to the states of the complex sampled inputs of a sampled signal epoch of interest. In this way, a more efficient and higher speed device is provided for the multiplication of complex variables.

Abstract: High-speed multifunction arithmetic arrays for multiplication, division, square and square-root operations are presented in this paper. These arrays seem attractive due to their versatility and speed. A recently described quotient-bit evaluation technique that uses the carry-save method in a nonuniform division array is extended here for the restoring-division process. This array includes the multiplication process as well, and the division time approaches that of multiplication. The design objective of multifunctional arithmetic arrays precludes consideration of other high-speed division techniques. A further extension of the restoring division process is shown to make the design of an array for square/square-root operation straightforward. The two underlying arrays can be coalesced to perform any one of the four operations. Possible methods of merging the arrays, with their relative merits, are also discussed. For illustration purposes, complete internal details of such a generalized pipelined array for 4-bit operation is included in this paper. Due consideration is also given to the possibility of large-scale integration of the different arrays illustrated in this paper.

Abstract: This paper presents a class of algorithms, On-Line Continued Sums/Products, which are amenable for the efficient implementation by a pipeline architecture. The implementation of these algorithms provides a simple and fast method for the evaluation of several of the elementary functions; i.e., addition, subtraction, multiplication, division, logarithm, exponentiation, sine, cosine, and tangent. In addition to possessing the expected properties necessary for the efficient implementation in a pipeline architecture, the On-Line Continued Sums/Products algorithms allow for the possibility of implementing a pipeline architecture which is dynamically reconfigurable and which can process variable precision operands.

Abstract: Two new families of LSI iterative logic arrays are proposed to perform two's complement multiplication based on the Baugh–Wooley algorithm [2]. The global approach is faster and attractive for LSI but limited in size due to current monolithic and packaging technology. The modular approach is better suited to realizing arbitrarily large array multipliers at only slight decrease in speed. The proposed additive multiply modules can be externally programmed by hardwiring to multiply binary numbers in either two's complement or unsigned format. No peripheral logic circuits such as Wallace trees or complementers are needed in constructing the proposed modular multiplication networks. Speed analysis, hardware complexity, packaging, and application requirements of the proposed array multipliers are also provided.

Abstract: A multiplication is constructed which extends the vector space structure of Eucidean n-space to a commutative algebra.

Abstract: This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry, systems or the like wherein elongated information trains represented by multiple words of multiple bits are multiplied by equally long information trains. In many cases, the trains comprise a plurality of trailing zeros which, in accordance with the operation of this circuit, can be detected whereby the multiplication operation can be significantly speeded by avoiding unnecessary multiplication by zeros without loss of accuracy.

Abstract: We study the power of RAM acceptors with several instruction sets. We exhibit several instances where the availability of the division operator increases the power of the acceptors. We also show that in certain situations parallelism and stochastic features ('distributed random choices') are provably more powerful than either parallelism or randomness alone. We relate the class of probabilistic Turing machine computations to random access machines with multiplication (but without boolean vector operations). Again, the availability of integer division seems to play a crucial role in these results.

Abstract: A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible combinations of one group of the first number and one group of the second number are formed, for each combination a partial product being formed in a first array of partial product forming devices. A partial product is preferably formed by a logic circuit which operates non-sequentially but exclusively combinatory, and which has a logical depth of only three gates. The partial products are subsequently applied to a second array of partial sum forming devices in which they are added together with intermediate partial sums, taking into account their relative significance levels. Together with the partial product digit of lowest significance, the final row of partial sum forming devices then generates, co-operating in parallel, the complete product. A corresponding method can be used for the multiplication of binary numbers in two's complement representation. In that case the product of the parts after the decimal point must be increased by the cross products of the parts before the decimal point and the inverted values of the parts of the two numbers after the decimal point. The part of the product before the decimal point is obtained by modulo-2 addition of the parts before the decimal point of the two number in two's complement representation itself.

Abstract: A new method for implementing frequency multiplication of square waves is presented. It is simpler and more flexible than any other method. The frequency multiplication parameter n can be programmable, therefore there is no need to change hardware when the parameter n is varied. In particular. the accuracy of the output square wave can be improved easily by increasing the reference frequency, in contrast with the conventional method which is subject to practical limitations, such as the linearity of the IC elements, especially the integrator.

Abstract: A multipurpose optical moire processor is described whereby one can introduce mismatches fringes, perform fringe multiplication and shifting, and separate u- and v-field isothetics. These functions can be done individually, sequentially, or simultaneously.

Abstract: A multiplication study device for teaching a student multiplication skills by operation of push-buttons mounted in a box-shaped case. The push-buttons are each provided with a semi-transparent see-through surface which permits the appearance therethrough of an answer to a multiplication problem when the push-button is depressed so as to come into contact with a projecting member disposed therebelow. A plurality of the push-buttons are mounted in the case, and the case includes a rear cover for mounting the projecting members. A common resilient member in the form of a urethane plate is employed for normally urging the push-buttons in an upward direction.

Abstract: A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q 1 +Q 2 ×2-n (Q 1 , Q 2 : binary numbers). The binary numbers Q 1 and Q 2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q 1 is used as a part of the data for performing the division processing of Q 2 , thus effectively transferring any error evolving during the processing of Q 1 to Q 2 . The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

Abstract: The best strategy for extension of the oncostatic arsenal depends on the development of analogs of the present effective agents. Several analogs of an active family may have different toxicities [9, 25; Mori et al., unpublished data] and experimental and clinical tumors may present different primary [4, 11] or secondary resistance to different analogs [5, 16, 19]. Thus having two active analogs may be equivalent to having two families available. Ideally, experimental pharmacologists should be able to provide the clinician with new analogs that have a higher antitumoral activity and or lower toxicity than the ones currently available, or which are not cross-resistant with them. But how can the oncostatic effects and the toxicity of analogs be compared experimentally? A look at how experimentalists and clinicians compare analogs suggests that there are too many methods, all imperfect in varying degrees. We have learned by experience that the in vivo experimental screening tests used routinely to assess the oncostatic potential of a drug do not give a very accurate prediction of its clinical usefulness. Every year only a few experimentally active drugs reach the point of clinical trials, and still less are shown to be active and useful in man. Furthermore, it has not been possible to predict the spectrum of activity of the drugs on human tumors experimentally [24]. In vitro tests are even more inadequate. There is no consensus as to what cell lines should be used. All permanent lines are derived from highly selected cell clone(s), which is (are) in no way representative of the original tumor cells. As far as the various compounds are concerned, their solubility is often different, so that investigators very often have to use different solvents. Furthermore, the in vitro method is not valid when the oncostatic drugs work via their metabolites, as it is often

Abstract: PURPOSE: To reduce the overhead and attain the high speed operation by providing a construction forming a multiplication decimal multiple at the time of requisition. CONSTITUTION: The content of the multiple corresponding portion of the multiple accommodating register 12 is read by the multiple reading register 2 and then the presence or absence of the multiple is tested. If the multiple is correctly read (in the case of forming the test condition), the content enters the multiplication loop and the contents of the intermediate result accommodating register 1 and the register 2 are added by 6 and the result thereof is obtained by the register 1. Then, the value of the register 1 is shifted by 8 rightward by one column and the one shifted out column is, for example, stored as the calculation result to complete the operation of one column. In the case when the required multiple is not yet calculated, (in the case when the test condition is not established), one multiple of the multiplier is read to the register 2 and after the required multiple is obtained to the register 3 by using the work resist 3 and the decimal adding circuit 6, it enters the multiplication loop and thereafter the calculation is progressed hereinafter similarly. COPYRIGHT: (C)1981,JPO&Japio

Abstract: Algol 68 enables facilities for such things as arbitrary precision arithmetic to be provided in a particularly elegant and convenient way. The library segment mlaritha which provides such facilities is described. This segment enables numerical quantities to be stored and manipulated with almost the same degree of ease, or difficulty, as REAL quantities but with arbitrary and dynamically variable precision. The method of ‘NUMBER’ storage used in mlaritha is discussed in detail and the fundamental algorithms used for the arithmetic operations of addition, multiplication and division, etc., are described. Special attention is given to the ‘costs’ inherent in the use of the system; particularly in the time ‘costs’ of each of the operations and the dependence on precision.

Abstract: Large-scale integration has permitted the design of 4×4, 8×8 and even 16×16 multiplier systems on a single chip. This paper discusses methods of multiplication and identifies a method which is particularly suited to bit-slice integration and the multiplication of longer words such as 64 × 64 bits. A 2-bit slice has been designed on an uncommitted logic array, and these have been built into and tested in a 16 × 16 bit system. The results of the experiment are reported, and extrapolation from these show that a 64 × 64 bit multiplier can be built with 71 integrated-circuit chips to provide a multiplication time of less than 290 ns. Other developments are indicated which show that a reduction of these figures to 56 chips and 115 ns can be achieved. An alternative design using the same u.l.a. is found to be more expensive at 128 chips, but enables the time to be reduced to 80 ns. A number of other multipliers are also discussed, several of which would be an economical proposition as a high-performance add-on unit for many mini- and microcomputers. However, the u.l.a. design proposed here is found to be the most cost-effective system.