Abstract: The classical algorithms require order n ~ operations to compute the first n terms in the reversion of a power series or the composition of two series, and order nelog n operations if the fast Founer transform is used for power series multiplication In this paper we show that the composition and reversion problems are equivalent (up to constant factors), and we give algorithms which require only order (n log n) ~/2 operations In many cases of practical importance only order n log n operations are required, these include certain special functions of power series and power series solution of certain differential equations Applications to root-finding methods which use inverse mterpolauon and to queuemg theory are described, some results on multivariate power series are stated, and several open questions are mentioned

Abstract: This paper presents quantitative techniques for the evaluation and comparison of pipelined digital systems. They are based on three measures of effectiveness: delay, average time/operation, and average cost/operation. Moreover, the techniques do not assume that there is an unbounded stream of operations to be performed, although this case is considered. The use of the analysis methods to compare different ways of pipelining a given algorithm is illustrated by an investigation of the pipelining of general four-neighbor cellular arrays. The methods can also be used to evaluate different algorithms for performing the same operation. This is illustrated by comparing three array algorithns for integer multiplication.

Abstract: Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.

Abstract: A large class of multiplication problems in arithmetic complexity can be viewed as the simultaneous evaluation of a set of bilinear forms. This class includes the multiplication of matrices, polynomials, quaternions, Cayley and complex numbers. Considering bilinear algorithms, the optimal number of nonscalar multiplications can be described as the rank of a three-tensor or as the smallest member of rank one matrices necessary to include a given set of matrices in their span.In this paper, we attack a rather large subclass of three-tensors, namely that of $(p,q,2)$-tensors, for arbitrary p and q, and solve it completely in the case where the field of constants contains the roots of a polynomial associated with the given tensor. In all other cases, we prove that, in general, our bounds cannot be improved. The complexity of a general pair of bilinear forms is determined explicitly in terms of parameters related to Kronecker’s theory of pencils and to the theory of invariant polynomials. This reveals unexpect...

Abstract: The design criteria and implementation of the Arithmetic Element (AE) of the Burroughs Scientific Processor, a vector machine intended for scientific computation requiring speed of up to 50 million floating-point operations per second, is discussed. An array of 16 AEs operate in lockstep mode, executing the same instruction on 16 sets of data. The 16 AEs are one stage in a pipeline which consists of 17 memory modules, an input alignment network, and an output alignment network. The AE itself is not pipelined. It can perform over one hundred different operations including a floating-point addition, subtraction and multiplication, division, square root, among the others. Eight registers are provided for the storage of intermediate values and results. Modulo 3 residue arithmetic is used for checking hardware failures.

Abstract: The problem of high-speed multiplication is considered from the viewpoint of summand generation and summand summation. The goal is to obtain at least a 2's-complement, 32-bit floating-point (sign plus 24-bit fraction) multiplication in 10 to 20 ns using ECL LSI packages. Summand generation is implemented by mxm-bit multipliers. The optimum values for m are 9, 13, 17, or 21. Summand summation is implemented by a row of (p, 2) column-summing counters. The (3, 2), (5, 2), and (7, 2) counters are optimum choices. These counters compress p inputs into two outputs plus nonpropagating carry bits, where these bits are added to the next higher-order stage with at most two full adder delays.

Abstract: A microprocessor having the capability of performing either a multiply or divide operation from a single instruction for each operation is provided. Much of the standard circuitry of a microprocessor is used along with a multiply/divide cycle counter, logic circuitry, and a shift network separate from the arithmetic logic unit. The microprocessor has the capability of performing unsigned integer multiplication and division. A shift and add algorithm is used for multiplication while for division a non-restoring divide algorithm is used.

Abstract: The associativity problem for the class of finite multiplication tables is known to be undecidable, even for quite narrow infinite subclasses of tables. We present cri- teria which can be used to decide associativity in many cases, although any effective method based on such criteria must eventually fail on a table of some size (as other- wise decidability for the general class would follow). By means of an extensive com- puter search we have been able to use the criteria successfully to solve the associativity problem for all tables of order up to 3. We find 24,733 associative tables and 237,411 nonassociative tables, and present some further statistics about how "deep" we had to search to establish the nonassociativity of a table. We also prove that there are tables of order 3 for which no "one-mountain" theorem holds (which was known previously only for order 6 examples). Our methods make use of efficient data-representations and techniques of heuristic and adaptive programming.

Abstract: Apparatus for performing high-speed, parallel multiplication in a data processing system wherein each multiplication requires only one step to reduce a plurality of summands to two numbers whose summation equals the product. The fractional portion of two floating point numbers, the multiplier and the multiplicand, are coupled to registers. Thereafter, the multiplicand is multiplied by segments of the multiplier and the resultant products are summed together using a conventional shift and add means. The multiplicand and a segment of the multiplier are each coupled to a plurality of multiplier circuits which produce a plurality of summands. These summands are coupled to a plurality of counter circuits in a manner such that the digits of all of the summands representing the same power of the number 2 may be counted. The counters, using a table look-up scheme, generate two outputs which are coupled to two registers to form two numbers whose summation equals the product of the multiplicand and the segment of the multiplier.

Abstract: The effects which frequency multiplication produces on the power spectral density of an oscillator is examined as a function of the multiplication ratio and the power spectral density of the phase noise process. In addition, the power spectral density (PSD) of the multiplied-up oscillation is interconnected with the frequency standard L(f). It is explicitly demonstrated how errors are introduced when one attempts to define the rms fractional frequency deviation ?f(?)/f0 and the Allan variance ?2y(?) using the measurement of L(f). Finally, the genesis of spectral spreading of the PSD due to frequency multiplication is demonstrated in such a way that this interesting and important phenomena can be grasped by the practicing engineer.

Abstract: A “mental” multiplication scheme is given for the super hypercomplex numbers, which extend the 16-element Dirac algebra to 32 elements by appending the complex octonions. This extends the 5-vectors of relativity to 9-vectors. The problems with nonassociativity, for the group structures and wave equation covariance, are explored.

Abstract: The temperature dependence of multiplication noise in silicon avalanche photodiodes with a low-high-low impurity density profile is calculated. The variation of multiplication noise by temperature change can be neglected in practical use at a constant multiplication factor, which is in agreement with experimental results.

Abstract: The specific model of central or conscious processing system (CPS) is presented. It consists of two part: (1) a number of information carrying registers, and (2) a functional unit controlling the processes performed on the contents of the registers. The capacity limit is explained as a combination of storage capacity and processing capacity. The capacity limit was estimated by an experiment using mental multiplication performed according to a particular algorithm. The results suggested that the capacity was around eight to nine registers when the algorithm was strictly followed; this limit could, however, be exceeded because some problems automatically were coded and remembered by rules rather then by rehearsal. The results further suggested that information processing, i.e. the multiplication, had to take place on a time-sharing basis in competition with rehearsal, thus suggesting the existence of higher-order control system.

Abstract: The physical models traditionally used for introducing integers?thermometers, countdowns, and number lines?all have the deficiency that they do not aid in the teaching of all the operations with integers The number line has been a useful, if cum bersome, tool, but it cannot be used to demonstrate the multiplication of two neg atives This operation requires a formal proof, though special models have also been found to demonstrate it Martin Gardner (1977) describes two models for the multiplication of two negatives This article discusses a new model using positive and negative charges (see Bolster et al 1975) that can be used to develop operations with integers and which has been extended by a bright sixth grader in my class to cover multiplication of two negatives In the descriptions that follow, students manipulate positive and negative charges by using two different colored beans or chips They can also write them on their papers as + and ? charges For example, H) + Q=Qshows that +2 + "3 = "1 TKe best model for the teacher to use is bingo chips of two different colors on the overhead projector The advantages of using different-colored bingo chips on the over head projector are that the chips are color ful, transparent, and convenient in size; they can easily be moved, regrouped, and removed and replaced while at the same time allowing the teacher to write the equa tions that the chips illustrate In this article red chips represent positive charges and yellow chips represent negative charges My reason for selecting these colors is that my sixth-grade mathematics and science students have been exposed to these colors in their science textbooks as representing protons and electrons They are comfort able with the idea that a neutrally charged atom must have an equal number of posi tive and negative charges, and thus they experience no trouble with the analogous mathematical concept that the sum of op posites is zero This concept, that the sum of opposites is zero, is central to the model presented here, since all the other operations are based on it The following discussion is a con densation of a unit that progresses from the sum of opposites to the multiplication of negatives, at which point a teacher may decide to develop the model further to in clude the division of integers It is important that the students be ac tively involved in all the activities The teacher should provide the materials, state the problems, and then follow the students' recommended solutions until the satisfac tory ones are developed See table 1 for a discussion of the sum of opposites

Abstract: This paper deals with the problem of designing multiple-valued combinational functions and memory functions by complex modules It is shown how logical functions can be described by Postian vectors or by polynomials which are based on operations of the ordinary arithmetic such as addition and multiplication Two equations u = Sv and u' = Sv' are derived, by which all problems arising with two-level decomposition are solved The solution to these problems is demonstrated by two examples

Abstract: PURPOSE:To increase the transmission efficiency and to cope with the application for the digital network by packet exchange, by realizing both the character multiplication simultaneously in a high-speed data flow in accordance with the request of the terminal.

Abstract: On a ring or an algebra we introduce the quasi-multiplication a ⨂ b = ab + a + b, taking into account the multiplication and addition simultaneously. An example shows that this quasi-multiplication has remarkable and fundamental properties.

Abstract: All of the functions we have considered so far have been algebraic functions. An algebraic function is a function involving only the operations of addition, subtraction, multiplication, division, powers, and extraction of roots of expressions of the form a·x n , where a and n are real constants. Any function that is not algebraic is called a transcendental function. In this chapter, we will consider two important classes of transcendental functions, the exponential and logarithmic functions, as well as some applications of each.

Abstract: PURPOSE:To obtain a multiplication circuit of a simple structure, which gives a double multiplication to the frequency of a faint AC signal by amplifying and compounding the signal waveform appearing at the condenser which is connected in series between the input terminals.

Abstract: This paper presents the results of one phase of a study concerning methods for addition of P>2 numbers, each encoded as a vector of digits (digit vector) of length N. Such multi-operand addition has been studied most often in the context of reducing a set of partial products to a single result in the implementation of multiplication. More generalized multi-operand addition, most notably in the form of inner product calculations is, however, central to numerous scientific applications of digital computers. Although multi-operand addition is trivially accomplished by accumulation (iteration in time) in any general purpose machine, demands for very high-speed computation, typified by 2- and 3-D signal processing prompt implementation of dedicated, hardware-intensive structures for multi-operand addition. This study, for example, is motivated in part by requirements for rapid simultaneous addition of up to 100, 16-bit operands in the design of a dedicated processor for real-time reconstruction of 3-D images of the beating heart and breathing lungs [1].

Abstract: PURPOSE:To enable the digital overall areas passing circuit having less processing time, by reducing the multiplication circuit by one thru the increase in the number of registers.

Abstract: Compact arrangements of two-input magnetic bubble logic gates providing bubble devices for performing serial integer arithmetic on binary integers are disclosed. Using only a small number of different types of logic gates, designs are given for devices for performing serial addition, subtraction, multiplication and division arithmetic operations on binary integers, represented as sequences of magnetic bubbles. All logical interactions use bubble repulsion to prevent bubbles from transferring to adjacent propagation paths via preferred transitions. By using only two-input gates and a pipeline computational structure, hardware design is simplified and advantage is taken of the inherent serial nature of bubble technology. The simple gate interconnection geometry has a minimum of feedback paths and results in devices which are not burdened with excessive numbers of bubble generators, annihilators or crossovers.