Abstract: In this paper, on-line algorithms for division and multiplication are developed. It is assumed that the operands as well as the result flow through the arithmetic unit in a digit-by-digit, most significant digit first fashion. The use of a redundant digit set, at least for the digits of the result, is required.

Abstract: Interestingly, multiplication and division in mammalian cells that you really wait for now is coming. It's significant to wait for the representative and beneficial books to read. Every book that is provided in better way and utterance will be expected by many peoples. Even you are a good reader or not, feeling to read this book will always appear when you find it. But, when you feel hard to find it as yours, what to do? Borrow to your friends and don't know when to give back it to her or him.

Abstract: This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.

Abstract: This paper presents a new formulation of digital filters that combines the description of signal-processing and arithmetic operations. This is done by noting that multiplication is a form of convolution and therefore normal one-dimensional scalar convolution is in fact two-dimensional binary convolution. This is generalized to multidimensions and can be applied with table-look-up and transform techniques. The result is a unified description that describes a digital filter structure down to the bit level.

Abstract: The foundations are laid for a theory of multiplicative complexity of algebras and it is shown how “multiplication problems” such as multiplication of matrices, polynomials, quaternions, etc., are instances of this theory. The usefulness of the theory is then demonstrated by utilizing algebraic ideas and results to derive complexity bounds. In particular linear upper and lower bounds for the complexity of certain types of algebras are established.

Abstract: The characterizations of the closed ranges of the multiplication operators and the composition operators on L2 (λ) are reported in this paper.

Abstract: An FDM/TDM transmultiplexer uses sampling rate multiplication to increase the sampling rate for time division multiplexed (TDM) to frequency division multiplexed (FDM) conversion and decrease the sampling rate for FDM to TDM conversion. The rate multiplication filters are realized digitally in order to exploit the computational advantage of Fast Fourier Transform (FFT) algorithm, and channel filtering is implemented by a single time-shared sixth-order elliptic digital recursive filter. A novel FFT processor and recursive filter are disclosed which may be used in the system.

Abstract: This correspondence introduces a new number system, called the Focus number system which "focuses" on available resolution near zero much like an operational amplifier "focuses" on tiny deviations near virtual ground. This number system is supported by algorithms providing addition, multiplication, and higher order functions in a bare microcomputer at speeds rivaling those of existing integer arithmetic [1]-[3] performed with a costly arithmetic unit.

Abstract: PURPOSE: To easily adjust the lens group in the definite multiplication photography by servo-controlling shifting of the variable multiplication lens group in accordance with the focal distance such that an output multiplication of the multiplication count circuit amounts to a definite value. COPYRIGHT: (C)1978,JPO&Japio

Abstract: The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

Abstract: The present invention relates to a multiplication logic for signed multiplication of two numbers to obtain a double precision product in two's complement notation, each quantity being in serial form with the least significant bit first. The multiplier may be in either two's complement, sign magnitude, or unsigned notation, and the multiplicand in two's complement notation. With adjustment of a timing waveform, the multiplication logic will accommodate multiplicands of any word length and also various multiplier word lengths below a design maximum. With shorter multipliers, separate provisions are made for entry of the sign. The logic contains integrated timing responsive to the externally supplied timing waveform, a measure which simplifies application as operands are varied. The multiplication logic is suitable for use in a large number of digital applications including digital filters, correlation, convolution, squaring and polynomial evaluation. In addition to flexibility in the use of a given logic, repetitive cellular design permits larger or smaller logics to be readily produced. The design is suitable for large scale integration.

Abstract: A method for real-time matrix multiplication is presented. This paper describes the geometrical interpretation of the mathematical manipulations between the two matrices. Three coherent optical astigmatic systems are developed based on the analysis. Each system is essentially composed of two subsystems that are con-nected in series. The first one performs multiplications between the corresponding elements of the matrices coded in the amplitude transmittance of the transparencies. The results are received by the second subsystem that performs the necessary summation operations to give the calculated rise to each element in the final result, the product of the two matrices. In these processes, no preparation of a hologram or intermediate memory is required. The operations are done in parallel. The multiplication between an N x N matrix and an N x 1 vector is presented in detail. The possibility of multiplication between N x N and N x N matrices is also discussed.© (1977) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Abstract: In the paper a non-commutative algorithm for the multiplication of two square matrices of order n is presented. The algorithm requires n3-(n-1)2 multiplications and n3-n2+ 11 (n-1)2 additions. The recursive application of the algorithm for matrices of order nk leads to \(O(_n ^{k\log _n [n^3 - (n - 1)^2 ]} )\)operations to be executed.It is shown that some well-known algorithms are special cases of our algorithm. Finally, an improvement of the algorithm is given for matrices of order 5.

Abstract: The distance and speed measuring instrument uses a correcting device in the vehicle which consists of a division circuit, a multiplication circuit and a low-pass filter. The division circuit divides the number of distance pulses delivered by a wheel-independent measuring system by the number of distance pulses delivered by a wheel-dependent measuring system. The division result is smoothed with the low-pass filter and is then multiplied by a distance increment in the multiplication circuit.

Abstract: A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation. The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation. The least significant bit positions selected are used to read out the entire submultiple from the chip memories which thereafter are summed to produce a final product.

Abstract: The article describes a variable high-speed incremental computer that adopts the basic concept underlying a digital differential analyzer (DDA). Its structure closely resembles that of a microprocessor and includes the following features: floating-point arithmetic, a word-length transfer with the elimination of a residue (R) register, multibit multiplication, and a flexible software scheme of interconnections that includes the use of a stack to avoid redundant operations. The proposed structure has been simulated by solving a variety of differential equations with distinctly accurate results.

Abstract: The paper describes a scheme of a frequency multiplier that can be used for multiplying the frequency by n times. By connecting such m circuits in sequence it is possible to achieve frequency multiplication of mn.

Abstract: This paper describes a new magnetic decimal scaler as a universal arithmetic module (UAM) realized by expanding the function of the multi-level magnetic scaler. In order to implement pulse-train signal processing systems, three arithmetic operations (addition, multiplication and delay) are required. The proposed UAM has adder, multiplier and delay functions, all in one. So the pulse-train signal processing systems can be implemented by using only UAM's as a basic building block. This results in high reliability and simplicity with respect to the operation and construction of the systems, as compared with the case using commercially available binary-circuits.

Abstract: PURPOSE: To attain a real-time picture process through high-speed multiplication and division among various arithmetic processes performed in the process of reading from a picture memory and displaying, by providing an arithmetic part between a screen memory and display part. COPYRIGHT: (C)1978,JPO&Japio

Abstract: PURPOSE:To realize CPU back-up system through which CPU is tripled and CPU's fault can be detected at an early stage through decision by majority and with no help of software to continue driving by cutting off the fault instantaneously, and thus to secure an effective use for the electronic exchange, etc.

Abstract: PURPOSE:To perform time division multiplication and demodulation with simple structure using light fiber of different light path lengths.

Abstract: The optimality of the binary algorithm to evaluate xn is established where x is an integer or a completely dense polynomial modulo m, n is a positive integer, and the multiplications are done using a simple improvement on the naive algorithm.