Abstract: In this paper we are considering problems of division and multiplication in a computational environment in which all basic arithmetic algorithms satisfy "on-line" property: to generate jth digit of the result it is necessary and sufficient to have argument(s) available up to the (j+δ)th digit, where the index difference 6 is a small positive constant. Such an environment, due to its potential to perform a sequence of operations in an overlapped fashion, could conveniently speed up an arithmetic multiprocessor structure or it could be useful in certain real-time applications, with inherent on-line properties. The on-line property implies a left-to-right digit-by-digit type of algorithm and consequently, a redundant representation, at least, of the results. For addition and subtraction such algorithms, satisfying on-line property, can be easily specified. Multiplication requires a somewhat more elaborate approach and there are several possible ways of defining an on-line algorithm. However, the existence of an on-line division algorithm is not obvious and its analysis appears interesting.

Abstract: An important component of mechanical theorem proving systems are unification algorithms which find most genaral substitutions which, when applied to two expresssions, maka them equivalent. Functions which are associative and commutative (such as the arithmetic addition and multiplication functions) are often the subject of mechanical theorem proving. An algorithm which unifies terms whose function is associativa and commutative is presented here The algorithm eliminates the need for axiomatizing the associativity and commutativity properties and returns a complete set of unifiers without recourse to the indefinite generation of vurianU and instances of the terms being unified required by previous solutions to the problem.

Abstract: A method for designing the read-only memories (ROM's) needed for multiplication using logarithms is developed. By defining the word length of the multiplicand, multiplier, and product as n bits and the word length of -the rounded logarithms as m bits, design curves are given that allow various values of n and m to be selected for a given multiplier accuracy. Then a table is used to determine, which combination results in an implementation with the least number of bits.

Abstract: Spiroplasmas, helical motile wall-free prokaryotes, have only recently been recognized as a distinct new group of microorganisms' referrable to the Mollicutes?. a but meriting an assignment to a new family within the class.' In the past, spiroplasmas were regarded as spirochetes by workers who observed them in the hemolymph of insects, as viruses by workers who observed the symptoms of plant diseases they induced, or as mycoplasmas by workers who used thin-section electron microscopy for their visualization. Only one spiroplasma (Spiroplasma citri) has been assigned a Latin binomial, but techniques derived for its culture 6. have enabled its repeated isolation, and many strains from diverse geographic locations are now available for laboratory study. Some of these strains were shown to multiply in leafhoppers,s, 0 and eventually these insects were used experimentally to transmit the agent to citrus and other plants.l0, l1 Also, the agent could be cultured from two leafhopper species in the field,'? one of which, Circulifer tenellus (Baker), is already well known for its ability to transmit the destructive beet curly top virus. The other insect, Scaphytopius nitridus (DeLong) , breeds on citrus and can acquire and transmit the pathogen.'3 Progress in the culture of two other spiroplasmas has been less rapid. The sex ratio organism (SRO) of Drosophila was discovered 1 4 as a result of its ability to eliminate male progeny from female flies in which it is inherited maternally. Actually, there are several SROs, each of which was isolated from different but closely related neotropical species of Drosophila but which can be differentiated by differential susceptibility to lysis by strain specific viruses. At first, the SRO was considered to be a spirochete,\" but it was later shown ' 5 . l6 to lack an axial filament and an outer envelope or cell wall; both structures are characteristic of spirochetes. The SRO, then, appears, to possess features more similar to the spiroplasmas than to the spirochetes. In addition, antiserum

Abstract: Observations are made on the effect of pipelining iterative arrays for multiplication. It is suggested that the best type of latched array for multiplication is the save-carry iterative array. The effect of pipelining on other iterative arrays, including the general multiply/divide array is discussed.

Abstract: A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication. The circuits are related to each other and to contemporary circuit algorithms in the course of the syntheses and in a comparative discussion. Circuits with complemented multiplier/multiplicand (M) or complemented partial product word (P) corrections offer advantages in circuit symmetry and algorithmic structure.

Abstract: A multiplication apparatus comprises a plurality of multiple generator circuits, each of which simultaneously generates binary signals representative of a predetermined multiple of a multiplicand for different digits of a group of multiplier digits. A different one of the multiple generator circuits couples to a different one of a plurality of serially connected adder circuits for applying the binary signals. Each of the multiple generator circuits includes storage circuits coupled to receive timing signals from a common source to enable an overlap in the generation of binary multiple signals minimizing the number of multiplication cycles required to perform a multiplication operation in response to multiply instructions.

Abstract: Canonical forms for m-valued functions referred to as m-Reed–Muller canonical (m-RMC) forms that are a generalization of RMC forms of two-valued functions are proposed. m-RMC forms are based on the operations ⊕m (addition mod m) and .m (multiplication mod m) and do not, as in the cases of the generalizations proposed in the literature, require an m-valued function for m not a power of a prime, to be expressed by a canonical form for M-valued functions, where M > m is a power of a prime. Methods of obtaining the m-RMC forms from the truth vector or the sum of products representation of an m-valued function are discussed. Using a generalization of the Boolean difference to m-valued logic, series expansions for m-valued functions are derived.

Abstract: Circuits for performing arithmetic operations using base –2 representations are considered. Study of the counting process leads to a negative binary up-down counter and new simple methods for positive-negative base conversions. The advantage of employing carry-borrow rather than carry-only during additions is pointed out. Certain special features of negation, arithmetic shift, multiplication, and division in base –2 are described.

Abstract: A multiplier for multiplying a fixed point multiplicand by a floating point multiplier utilizes decode logic which provides control signals related to two numbers, the sum of which is approximately equal to the mantissa of the multiplier. The multiplicand is separately left shifted in two circuits, responsive to the control signals, by a number of places respectively corresponding to the values of said two numbers. The shift circuit outputs are summed algebraically in an adder. The sum is then shifted by a number of places and in a direction determined respectively by the magnitude and sign of the power of the floating point multiplier. The result is a close approximation of the desired multiplication product. The multiplier advantageously is employed in an electronic musical instrument.

Abstract: This letter discusses an organization of an approach to form the inner product of a pair of data vectors. The criterion is the minimization of the number of adders, the independent variable is the number of bits to be formed in the product. The cost ratio of addition-to-storage provided the motivation for this investigation. The most efficient mechanization appears to be the combining of the vectors in sets of 3 or 4 elements at a time, then summing the results.

Abstract: The growth of callus tissue from adult A. andraeanum plants was best in a modification of Murashige and Skoog's medium. On this medium genotype A 42-3 reached a fresh weight multiplication rate of 30.7 when grown for 5 weeks at a rotation speed of 120 rev/min, at 25 deg C and in continuous darkness. The fresh weight multiplication rate of 6 other genotypes of the same species varied considerably when grown on the best medium for A 42-3. (Abstract retrieved from CAB Abstracts by CABI’s permission)

Abstract: PURPOSE: At the time of receiving broadcast of FM, to prevent click noises due to variations of elements in the multiplication apparatus by making the output of le left and right channels short and released under the condition that sub-carrying wave remains applied to the double balance type multiplication apparatus. COPYRIGHT: (C)1977,JPO&Japio

Abstract: A new version of the source-multiplication method for measuring subcritical reactivities is presented. It does not require calibration against an independent reactivity measurement and can be appli...

Abstract: PURPOSE: The encoded picture signal element of no correlation between frames is inserted in terms of time division multiplication into coded pictue signal element with correlation between frames. As a result, picture can be transmitted very effectively. COPYRIGHT: (C)1977,JPO&Japio

Abstract: Recently, Langham proposed an original technique for frequency multiplication. His circuit uses two oscillators and a simple digital processor. One of the oscillators serves for measuring the period of the input waveform, the other determines the period of the output waveform. The multiplication factor of this frequency multiplier is equal to the ratio of the frequencies of the two oscillators. This circuit has certain advantages when compared to conventional frequency multipliers: it is capable of multiplying the input frequency by any positive real rational number, and yet it is an open-loop system, inherently stable and capable of tracking even the fastest changes in input frequency. One of its main drawbacks is the direct dependence of the accuracy and stability of its multiplication factor on the tracking characteristics of two independent oscillators. A way of eliminating this drawback is proposed here. It involves discarding one of the reference oscillators at the cost of adding a readonly memory (ROM). The modified system is insensitive to reference frequency variations and its accuracy is determined only by the roundoff errors in the digital processor.

Abstract: A competitive board game in which two playing boards are used and a set of 117 tiles for placement upon the playing boards, the playing boards having spaces where the tiles are to be placed, some of the tiles having arithmetic addition, subtraction, multiplication and division symbols while other of the tiles have the numerical digits, the game using arithmetic so to be played.

Abstract: Two algorithms that solve the frequently occurring problem in computer graphics, windowing, are described. The primary distinction between the two algorithms is the need for multiplication and division in one of them. The algorithms are compared for running time and size on two commonly used minicomputer systems, the Digital Equipment Corporation PDP-9/15 and PDP-11. Not surprisingly the algorithm incorporating the extended arithmetic capability executes faster and the PDP-11 versions are substantially smaller.

Abstract: A recently proposed method to implement digital filters using ROM can also be employed to implement multiplication by a constant. This note discusses alternate implementations for digital filter sections substituting memory for logic and points out the possible advantage of doing so.

Abstract: A method of and apparatus for fast digital multiplication wherein the lowest-weight digits and the high-weight digits which are equal to zero and whose weight is greater than the first high-weight digit equal to 1 are removed. The apparatus and method may be utilized in digital frequency filters.

Abstract: Array-like structures for high-speed multiplication, division, square and square-root operations have been described in this paper. In these designs the division and square-rooting time have been made to approach to that of multiplication operation. These structures are optimum from speed and versatility point of view. Most of the cellular arrays described in the literature are adequately slow. The time delay is particularly significant in the division and square-rooting operations due to the ripple effect of the carries. Though the carry-save technique has been widely utilized for multiplication operation, it has been only recently employed by Cappa et. al. in the design of a non-restoring divider array. This requires sign-bit detection that makes the array non-uniform. Such an array has been named as an array-like structure. The carry-save method has been extended here for restoring division operation. Due to sign-detection and overflow correction requirements, the restoring method is slightly complex. But the main advantage of such restoring array is in its simple extension for multiplication operation. The array for the two operations, when pipelined, will have more computing power than all other multiplier-divider arrays. Suggestions have also been included for further speed improvement. The technique applied for division operation is as well applicable for the square-rooting and an array-like structure for square-square-rooting operations has also been given. For performing any one of the four operations, the only manipulation to be done is to combine the two arrays; one for multiplication-division and another for square-square-rooting. Possible methods of combining the two arrays have been indicated and their relative advantages and disadvantages have been mentioned. Finally, a generalized pipeline array-like structure with complete internal details and for 4-bit operation, has been shown. Due consideration has also been given to the possibility of large-scale-integration of different arrays presented in this paper.