Showing papers on "Multiplication published in 1974"
TL;DR: It is shown that arithmetic expressions with n ≥ 1 variables and constants; operations of addition, multiplication, and division; and any depth of parenthesis nesting can be evaluated in time 4 log 2 + 10(n - 1) using processors which can independently perform arithmetic operations in unit time.
Abstract: It is shown that arithmetic expressions with n ≥ 1 variables and constants; operations of addition, multiplication, and division; and any depth of parenthesis nesting can be evaluated in time 4 log2n + 10(n - 1)/p using p ≥ 1 processors which can independently perform arithmetic operations in unit time. This bound is within a constant factor of the best possible. A sharper result is given for expressions without the division operation, and the question of numerical stability is discussed.
942 citations
TL;DR: Baker-Campbell-Hausdorff formulas can be constructed simply by matrix multiplication as discussed by the authors, and examples are given in Section 2.2.1] and Section 3.
Abstract: Baker‐Campbell‐Hausdorff formulas can be constructed simply by matrix multiplication. Examples are given.
162 citations
TL;DR: In this article, a modification of Fermat's difference of squares method is used for factoring large integers, which permits factoring n in O(n I /3) elementary operations, where addition, subtraction, multiplication, division, or extraction of a square root is considered as an elementary operation.
Abstract: A modification of Fermat's difference of squares method is used for factoring large integers. This modification permits factoring n in O(n I /3) elementary operations, where addition, subtraction, multiplication, division, or the extraction of a square root is considered as an elementary operation. A principal part is played by the use of a dissection of the continuum similar to the Farey dissection. This has been programmed for n < 1.05 X 1020 on the CDC 6400.
88 citations
1 Jan 1974
TL;DR: A lower bound of cNlogN is proved for the mean time complexity of an on-line multitape with known upper bounds of the form cN(logN)k sub K, and for some classes the upper and lower bounds coincide.
Abstract: : A lower bound of cNlogN is proved for the mean time complexity of an on-line multitape. Turing machine performing the multiplication of N-digit binary integers. For a more general class of machines which includes some models of random-access machines, the corresponding bound is cNlogN/loglogN. These bounds compare favorably with known upper bounds of the form cN(logN)k sub K, and for some classes the upper and lower bounds coincide. The proofs are based on the 'overlap' argument due to Cook and Aanderaa. (Author)
50 citations
TL;DR: An algorithm is presented here which implies that every polynomial of degree n with at most s distinct coefficients can be realized with O(n/\log _s n) operations.
Abstract: Many problems, including matrix-vector multiplication and polynomial evaluation, involve the computation of linear forms An algorithm is presented here which offers a substantial improvement on the conventional algorithm for this problem when the coefficient set is small In particular, this implies that every polynomial of degree n with at most s distinct coefficients can be realized with $O(n/\log _s n)$ operations It is demonstrated that the algorithm is sharp for some problems
50 citations
42 citations
TL;DR: A generalized pipeline cellular array has been proposed which can perform all the basic operations such as multiplication, division, squaring, and square rooting and it has been shown that these arithmetic operations can be overlapped in the pipe in any desired sequence, and thus significant speed improvement can be achieved.
Abstract: A generalized pipeline cellular array has been proposed which can perform all the basic operations such as multiplication, division, squaring, and square rooting. The different modes of operation are controlled by a single control line. An expression for time delay has been obtained. Further, it has been shown that these arithmetic operations can be overlapped in the pipe in any desired sequence, and thus significant speed improvement can be achieved. The array is fully iterative and hence is suitable for large-scale integration (LSI).
35 citations
Patent•
1 Apr 1974TL;DR: In this paper, an array of 3-bit adders is constructed from a combination of threshold logic modules, and the resulting simplifications permit circuit realization in the form of an array.
Abstract: Apparatus and methods for performing the parallel m-bit by n-bit multiplication of two binary 2's complement numbers by converting the multiplication process to an equivalent parallel array addition in which the operands are positive partial products including (1) terms formed by ANDing a multiplier bit (or its complement), and (2) a multiplicand bit (or its complement) and five additional partial product terms. The resulting simplifications permit circuit realization in the form of an array of 3-bit adders each formed from a combination of threshold logic modules.
21 citations
TL;DR: In this paper, the authors construct all semirings with a given completely simple additive semiroup ℳ(G, I, ∧, P) by means of an associative and distributive multiplication on G, and associative multiplications on I and ∧ satisfying certain conditions.
Abstract: We construct all semirings with a given completely simple additive semiroup ℳ(G, I, ∧, P) by means of an associative and distributive multiplication on G, and associative multiplications on I and ∧ satisfying certain conditions.
20 citations
29 Jul 1974
TL;DR: Two additional schemes are discussed: minimal introduction of zero rows and columns, and permitting block multiplication as an additional tool in Strassen’s constant.
Abstract: Optimal use of either Strassen’s or Winograd’s algorithms for multiplying 2×2 matrices within the framework of Fischer and Probert yields only a relatively small reduction in Strassen’s constant of 47 Two additional schemes are discussed: minimal introduction of zero rows and columns, and permitting block multiplication as an additional tool The first scheme yields extremely small improvement, but the second turns out to be highly effective
TL;DR: A new algorithm for computing the correlation is presented, which is generally more efficient than FFT methods for processing 128 or fewer data points, or for calculating only the first L values of Rk, for L < 10 log2 2N.
Abstract: In this correspondence we present a new algorithm for computing the correlation [mi][/mi]. For applications where the "cost" of a multiplication is greater than that of an addition, the new algorithm is always more computationally efficient than direct evaluation of the correlation, and it is generally more efficient than FFT methods for processing 128 or fewer data points, or for calculating only the first L values of Rk, for L < 10 log2 2N.
TL;DR: This correspondence presents a simpler proof for Baugh and Wooley's two's complement parallel array multiplication algorithm, as demonstrated in a recent paper.
Abstract: This correspondence presents a simpler proof for Baugh and Wooley's two's complement parallel array multiplication algorithm, as demonstrated in a recent paper.1 The above algorithm converts a two's complement multiplication to an equivalent parallel array addition problem in which all partial product bits are positive.
30 Apr 1974
TL;DR: It is proved that by using parallelism the evaluation of any first order rational recurrence, e.g., [equation], and any non-linear
Abstract: This paper presents new algorithms for the parallel evaluation of certain polynomial expression. In particular, for the parallel evaluation of xn,we introduce an algorithm which takes two steps of parallel division and [log2n] steps of parallel addition, while the usual algorithm takes [log2n] steps of parallel multiplication. Hence our algorithm is faster than the usual algorithms when multiplication takes more time than addition. Similar algorithm for the evaluation of other polynomial expressions are also introduced. Lower bounds on the time needed for the parallel evaluation of rational expressions are given. All the algorithms presented in the paper are shown to be asymptotically optimal. Moreover, we prove that by using parallelism the evaluation of any first order rational recurrence, e.g., [equation], and any non-linear polynomial recurrence can be sped up at most by a constant factor, no matter how many processors are used.
Patent•
22 Nov 1974TL;DR: The signed multiplication logic as mentioned in this paper is composed of a plurality of largely identical multiplication cells which form partial products which are summed in largely identical summation cells to form the final product, which can be used to form single or double precision products.
Abstract: The present invention relates to signed multiplication logic for multiplying two serial binary numbers to obtain a serial binary product, the multiplicand containing magnitude and sign information in two's complement notation, the multiplier containing magnitude information, and the product containing magnitude and sign information in two's complement notation, all three bit streams occurring serially at equal word rates with the least significant bit first in time. The logic is composed of a plurality of largely identical multiplication cells which form partial products which are summed in largely identical summation cells to form the final product. Each multiplication cell stores a multiplier bit, contains a stage of a multiplicand shift register and a stage of a timing waveform shift register. Means are provided for truncation of the multiplicand and product rounding under timing waveform control. The logic is flexible and may be used to form single or double precision products. The design in utilizing two largely identical cells, with a minimum of communication paths at the cell and multiplication logic boundaries, is optimized for large scale integration using metal oxide semiconductor field effect transistor technology.
TL;DR: A method is described whereby an autocorrelation may be computed with slightly over half the usual number of multiplication operations.
Abstract: A method is described whereby an autocorrelation may be computed with slightly over half the usual number of multiplication operations.
Patent•
IBM1
TL;DR: In this article, a predicted residue is generated for each iteration by modifying the residue of the previous partial product according to the multiplier bits in the current iteration and the multiplicand residue.
Abstract: Apparatus for detecting multiplication errors in digital computers where multiplication is executed by iterative addition. A predicted residue is generated for each iteration by modifying the residue of the previous partial product according to the multiplier bits in the current iteration and the multiplicand residue. The current partial product is obtained and its residue generated. The generated current partial product residue is compared to the predicted residue for the current iteration to determine whether a hardware error has occurred. The process is repeated for each iteration, thereby eliminating the possibility of offsetting errors.
TL;DR: This paper presents detailed algorithms for the basic arithmetic operations on symbolic rational expressions represented by formal quotients of factored polynomials in the form of programs for equality-test, exponentiation, multiplication, and addition.
Abstract: In this paper we present detailed algorithms for the basic arithmetic operations on symbolic rational expressions represented by formal quotients of factored polynomials. These algorithms are currently implemented in the ALTRAN system for symbolic algebra but the descriptions given in this paper are system independent.First we describe the representation and examine the need for options to permit control over the amount of effort expended in the search for factors or in canonicalizing results. We then present algorithms in the form of programs for equality-test, exponentiation, multiplication, and addition, and mention the modifications required for division and subtraction.We conclude by presenting the results of several benchmark tests comparing the performance of these algorithms with others previously used.
TL;DR: An iterative method for zero-one minimization of integer polynomials, linear in each variable, is outlined, based on Camion's method of binary developments with computations using multiplication and sum mod 2.
TL;DR: The results show that the mode of multiplication in unstable spheroplast type L-form cells of E. coli K12 (λ) inst I does not only depend on some physical factors of the environment but also on the extent of disturbance in the cell envelope system.
Abstract: The multiplication of an unstable spheroplast type L-form of E. coli K12(λ) inst I was investigated by light microscopic and electron microscopic methods. The L-form cells were grown under the influence of penicillin in broth and on agar media. They show wall defects of different degrees. 5 types of multiplication could be differentiated morphologically: Multiplication by single site constriction, multiplication by multiple site constriction, multiplication by cell formation at the top of an outgrowth of cell wall and cytoplasmic membrane, multiplication by intracellular fragmentation as a result of asymmetric invagination of the cytoplasmic membrane, and multiplication as a consequence of fragmentation by formation of intracellular membranes. In larger cells different modes of multiplication can occur simultaneously. The results show that the mode of multiplication in unstable spheroplast type L-form cells of E. coli K12 (λ) inst I does not only depend on some physical factors of the environment but also on the extent of disturbance in the cell envelope system. Obviously, the cytoplasmic membrane and intracellular membranes play an important role in the multiplication processes.
TL;DR: A cellular-array multiplier based upon the use of `negabinary´ numbers is developed, a 4-quadrant multiplier, after the style of Napier's chequerboard, that requires no separate circuitry for sign manipulation.
Abstract: It is shown that a particular cellular-array multiplication technique used in integrated-circuit multipliers is equivalent to the chequerboard method of John Napier, the 16th-Century mathematician. Further, a cellular-array multiplier based upon the use of `negabinary´ numbers is developed. This is a 4-quadrant multiplier, after the style of Napier's chequerboard, that requires no separate circuitry for sign manipulation.
TL;DR: The advantages of a tree-like data structure for use in the multiplication of Poisson series by computer are espoused and computations with trees can be faster by a factor ofn/log(n), wheren is the number of trigonometric terms in a multiplicand.
Abstract: The advantages of a tree-like data structure for use in the multiplication of Poisson series by computer are espoused. Compared to list representations, computations with trees can be faster by a factor ofn/log(n), wheren is the number of trigonometric terms in a multiplicand.
Patent•
9 Jan 1974
TL;DR: In this paper, an oscillator with built-in compensation means is used to provide compensating deviations in each of the frequency outputs to eliminate deviations in the resulting beat frequency. But the compensation mechanism is limited to a single oscillator.
Abstract: Oscillator devices for generating signals of a precise frequency. The device produces two outputs of differing frequencies. The two signals are combined to develop a beat frequency representing the difference therebetween. The device has built-in compensation means to provide compensating deviations in each of the frequency outputs to eliminate deviations in the resulting beat frequency. Frequency division and/or multiplication of the discrete generated signals is employed to obtain the desired precise beat frequency.
Patent•
12 Sep 1974TL;DR: In this article, change-over switches at positions of the shift register conforming to binary ones of the multiplier are used to enable serial multiplication of a binary multiplicand with a binary multiplier.
Abstract: In the case of a calculating unit for serial multiplication of a binary multiplicand with a binary multiplier, the multiplicand is inserted into a shift register in serial form. The development of the product is achieved by suitably providing change-over switches at positions of the shift register conforming to binary ones of the multiplier. The product is filled with the sign digit to the required number of digits by the change-over switches which then connect the output with a sign register.
Journal Article•
TL;DR: In this article, an analysis is made of the possibility of construction of arithmetic units based on the passage of light signals through electric-field-controlled optical transparencies, which can perform any Boolean algebraic operations.
Abstract: An analysis is made of the possibility of construction of arithmetic units based on the passage of light signals through electric-field-controlled optical transparencies. Such arithmetic units can perform any Boolean algebraic operations. Methods for performing the basic arithmetic operations (addition, subtraction, multiplication, and division) are described. A brief discussion is given of the block diagram of an optoelectronic arithmetic unit with a speed of several tens of millions of algorithmic operations per second.