TL;DR: Applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.
Abstract: An approximate method for rapid multiplication or division with relatively simple digital circuitry is described. The algorithm consists of computing approximate binary logarithms, adding or subtracting the logarithms, and computing the approximate anti- logarithm of the resultant. Using a criteria of minimum mean square error, coefficients for the approximations are developed. An error analysis is given for three cases in which the algorithm is useful. Finally, applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.
TL;DR: The use of redundant number systems and the design of a structure with which multiplication and division are executed radix 256, which is a recently discovered member of the family of borrow-save subtracters and carry-save adders.
Abstract: In keeping with the experimental nature of the Illinois Pattern Recognition Computer (ILLIAC III), the arithmetic units are intended to be a practical testing ground for recent theoretical work in computer arithmetic. This paper describes the use of redundant number systems and the design of a structure with which multiplication and division are executed radix 256. The heart of the unit is the stored-sign subtracter, a recently discovered member of the family of borrow-save subtracters and carry-save adders. A cascade of these subtracters, controlled by a multiplier recoder, provides multiplication. The same structure, controlled by a "model division" (a quotient recoder), performs division.
TL;DR: In this paper, an arithmetic unit for accomplishing the multiplication of two binary numbers at high speeds is described, and a modification of the basic system provides for the simultaneous combination of the multiplicand with a plurality of individual multiplier digits to reduce the number of stages required in the apparatus.
Abstract: An arithmetic unit for accomplishing the multiplication of two binary numbers at high speeds is described herein. By utilizing a plurality of gates connected in successive stages, the combinations of individual digits of a multiplicand and a multiplier to produce the product thereof is accomplished. The gates of the successive stages are so connected as to shift the partial product produced at each stage by one digit to the right, the least significant digit of that stage being shifted out as a product digit. In the simplest case, there will be as many stages as there are multiplier digits. However, a modification of the basic system provides for the simultaneous combination of the multiplicand with a plurality of individual multiplier digits to reduce the number of stages required in the apparatus. Each stage produces carries which are added in by means of inter-spaced adders or half-adders at each stage. No timing signals are required since this apparatus operates as an asynchronous device. Therefore, each stage occupies only the time required to transfer the function through it, and the total multiplication process is speeded up thereby. The modification which permits simultaneous combination of a plurality of multiplier digits with the multiplicand shortens the required multiplication time even further, and if special encoders are utilized, the total multiplication time can be even further reduced. Since no timing pulses are required, information flows through the multiplier as a ripple.
TL;DR: A recent survey of journal articles published in the United States on research in elementary school mathematics since 1900 (Suydam, 1967) listed only nine studies on multiplication, three of which were classified as experimental.
Abstract: A recent survey of journal articles published in the United States on research in elementary school mathematics since 1900 (Suydam, 1967) listed only nine studies on multiplication, three of which were classified as experimental. None of these attempted to analyze in depth the strategies used by children to find the product of simple combinations. The comprehensive study on the learning of multiplication facts conducted by Brownell and Carper (1943) included a critical analysis of existing research that led them to conclude little was known regarding strategies children used in solving the multiplication combinations. Brownell and Carper, however, did attempt to discover processes children were using to solve multiplication problems, though the results were not entirely satisfactory. Through personal interviews, conducted by teachers according to well-defined outlines, children were asked to tell how they "thought about" several different problems. It was reported that the children interviewed used a mean of four different strategies in arriving at the product of the combinations used in the interviews, although 60% of the strategies used remained unidentified, i.e., classified as rote memory or habituation. Historically, the major thrust in research has been to determine which combinations are the most difficult and to attempt to identify strategies either by analysis of errors (e.g., Spencer, 1929) or by rank-ordering combinations in terms of probability of correctness (e.g., Clapp, 1924; Murray, 1939) and to devise ways to teach them that would facilitate learning and retention. Murray (1939) compared his own ranking of relative
TL;DR: Slices from three-dimensional frozen-stress models were collected from numerous photoelastic laboratories and these diverse samples were used to demonstrate fringe multiplication Multiplied isochromatic patterns of excellent clarity and fidelity are presented Maximum multiplication factors of 9 or 11 are exhibited for most demonstrations, but multiplications by 17 and 25 are exhibited in special cases Speed, accuracy and simplicity of the method are discussed, and benefits of full-field data retrieval are emphasized as mentioned in this paper.
Abstract: Slices from three-dimensional frozen-stress models were collected from numerous photoelastic laboratories and these diverse samples were used to demonstrate fringe multiplication Multiplied isochromatic patterns of excellent clarity and fidelity are presented Maximum multiplication factors of 9 or 11 are exhibited for most demonstrations, but multiplications by 17 and 25 are exhibited for special cases Speed, accuracy and simplicity of the method are discussed, and benefits of full-field data retrieval are emphasized
TL;DR: In this paper, a graphical method is presented, which allows the determination, for a p - n junction, of the breakdown voltage and also the electric field distribution, the width of the depletion layer and the multiplication factor, all at a given reverse voltage.
Abstract: A graphical method is presented, which allows the determination, for a p - n junction, of the breakdown voltage and also the electric field distribution, the width of the depletion layer and the multiplication factor, all at a given reverse voltage. This method is based on the approximation of the exact impurity profile by an exponential function. The use of reduced parameters makes the method independent of the material. Numerical examples are presented.
TL;DR: The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion.
Abstract: This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion.
TL;DR: A graph model is developed which permits a translation of the given arithmetical algorithm into an interconnection diagram of ABE's, and for the evaluation of the cost and speed for a given polynomial degree and a given precision requirement.
Abstract: The advent of large-scale integration of logic circuits requires the definition of digital computer structure in terms of large functional arrays of logic of very few types. This paper describes a single-package arithmetic processor called the arithmetic building element (ABE). The ABE accepts operands in either conventional or signed-digit radix-r representation and produces signed-digit results, which the ABE can reconvert to conventional form. Radix 16 is chosen for illustrations. Arrays of ABE's may be arranged to implement unit- time parallel addition, all-combinational multiplication, and more complex functions which are presently computed by subroutines. To facilitate such arithmetic design, a graph model is developed which permits a translation of the given arithmetical algorithm into an interconnection diagram of ABE's. The design procedure is illustrated by an array for polynomial evaluation. Speed, cost, and roundoff error of the array are considered. A computer program has been written for the automatic translation of the algorithm graph to an interconnection graph, and for the evaluation of the cost and speed for a given polynomial degree and a given precision requirement.
TL;DR: In this article, a signal processor utilizing the auto-correlation technique for detecting a signal in the presence of noise is presented, which reduces both the required time delay and integrating time in conventional auto correlation processes by the use of a (N) by (M) matrix analog correlator.
Abstract: A signal processor utilizing the auto-correlation technique for detecting a signal in the presence of noise. The device reduces both the required time delay and integrating time in conventional auto-correlation processes by the use of a (N) by (M) matrix analog correlator. The device accepts noise and signal which are assumed to be statistically independent and by linearly multiplying both (N) reiterated times and filtering out the d.c. or base band products from each multiplication, forms the final function for correlation. This process of linear multiplication is repeated over (M) parallel paths. The (N) reiterated linear multiplications reduce the required time delay to a small fraction. The (M) parallel paths reduce the required integrating time also to a very small fraction.
TL;DR: A function f(, ) of two variables is said to be separately continuous if for each fixed y and each fixed x, the functions f(, y) and f(x) are continuous functions of one variable.
Abstract: A function f( , ) of two variables is said to be separately continuous if for each fixed y and each fixed x, the functions f(, y) and f(x,) are continuous functions of one variable. Separately continuous functions seem to be playing a larger role in analysis than formerly. In (1) there is an account of the theory of semigroups in which the multiplication is separately continuous, and in (9) various analytic theorems are obtained by the study of separately continuous functions f(s, t), where t ranges over a set T, and s ranges over a set of functions on T.
TL;DR: A more efficient and novel approach of a scalar multiplication method than the double-and-add by applying redundant recoding which originates from the radix-4 modified Booth’s algorithm, which is called the novel algorithm quad- and-add.
Abstract: The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the topmost level of GF multiplication and GF division, has been the double-and-add algorithm, which is being recently challenged by NAF (Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel approach of a scalar multiplication method than the double-and-add by applying redundant recoding which originates from the radix-4 modified Booth’s algorithm. We call the novel algorithm quad-and-add. After deriving the algorithm, we created a new GF operation, named point quadruple, and verified with calculations of a real-world application to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language). Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.
TL;DR: In this article, the authors derived rules and procedures derived from the combinatorial properties of the $k$-statistics and other symmetric functions linearly related to them.
Abstract: The multiplication of $k$-statistics is treated by Fisher [4], Tukey [8], [9], Wishart [10], Kendall [5], Abdel-Aty [1], Dwyer and Tracy [3], and Tracy [7]. Various rules, procedures, functions and tables have been devised to aid in this task. The rules and procedures derived from the combinatorial properties of the $k$-statistics and other symmetric functions linearly related to them. When dealing with generalized polykas is was found convenient to ignore communtativity of multiplication in denoting the various symmetric functions and use ordered partitions to represent them rather than the usual partitions [2]. The simplicity of the relationships among the symmetric functions, which results from the use of ordered partitions, may be used to obtain simple multiplication procedures.
TL;DR: This work generalizes that circuit construction method for group multiplication requiring time at most one unit greater than the lower bound so as to render it applicable to any function f:X"1 x X"2 -> Y, where X"1 andX"2 are finite sets.
TL;DR: In this article, the multiplication of whole numbers is seen in terms of a street-crossing model, where if there are 4 + streets and 3 I streets, there are four x 3 intersections or crossings.
Abstract: Following are some brief comments on an approach to multiplication of whole numbers. The approach, while not new, has not been widely used with young children, and it is a possibility that the development suggested herein may offer some advantages over the various approaches in current use. In the present approach, multiplication of whole numbers is seen in terms of a street-crossing model. If there are 4 ?-+ streets and 3 I streets, there are 4 x 3 intersections or crossings. 3
TL;DR: A BCD to binary converter in which a plurality of shift registers receive BCD inputs in parallel and the outputs of each shift register is serially passed through 10-times multipliers until the proper decimal level is reached is described in this paper.
Abstract: A BCD to binary converter in which a plurality of shift registers receives BCD inputs in parallel and the outputs of each shift register is serially passed through 10-times multipliers until the proper decimal level is reached; each of the 10-times multipliers being an addition of a two-times and eight-times multiplier and the sum of the next least significant digit being added after each multiplication.
TL;DR: This chapter illustrates the division operation using the set of natural numbers and presents stages that should be discussed with the class when division is being considered.
Abstract: Publisher Summary
This chapter illustrates the division operation using the set of natural numbers. Division can be defined in the terms of multiplication. Division can also be expressed in the terms of subtraction. Division can be understood through the concept of division and sets, division and multiplication, and division and subtraction. Division does not possess the commutative property. It does not possess the associative property. The chapter discusses the distributive property of division over addition. Division has the distributive property over addition only from the right. The chapter presents stages that should be discussed with the class when division is being considered. It is the best method to present division after other methods have been discussed. It has been found that children will soon omit recording much of the marginal work; they will rather do the calculations mentally.
TL;DR: In this article, a system using this property is described, which enables very high orders of frequency multiplication to be achieved, with minimum circuit complexity and maximum tolerance to component variation, by using an integral number.
Abstract: Frequency multiplication by an integral number is inherent in the spectrum of an angle-modulated wave. A system using this property is described, which enables very high orders of frequency multiplication to be achieved, with minimum circuit complexity and maximum tolerance to component variation.
TL;DR: The MULTIPLICATION CHECKLIST described in this article is part of a series being developed for use by teachers of youngsters of all ages who are studying basic mathematical operations.
Abstract: *Edward J. Scheffelin, Sacramento, California, is a mathematics consultant in private practice. Margaret A. Scheffelin, Ph.D., Sacramento, California, is on leave from California State College, Los Angeles, and is engaged presently in public service. THE MULTIPLICATION CHECKLIST described in this article is part of a series being developed for use by teachers of youngsters of all ages who are studying basic mathematical operations. Teachers can use the checklist as a curriculum framework for the following purposes. Discovering individual strengths and weaknesses under typical instructional conditions.
TL;DR: The design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations, based on the use of asynchronous cellular arrays is shown.
Abstract: Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.
TL;DR: This chapter presents an outline of some difficulties that arise with multiplication and inverting programs, when the elements are represented by words of abstract generators, and of some ways to overcome or avoid them.
Abstract: Publisher Summary This chapter focuses on calculation with the elements of a finite group given by generators and defining relations. The system of group theoretical programs working at Kiel consists of programs that are independent of, and others that depend on, the special way in which the elements of the group to be calculated are represented. The latter are concerned with reading the input data and printing, multiplication of, and inverting elements. This chapter presents an outline of some difficulties that arise with multiplication and inverting programs, when the elements are represented by words of abstract generators, and of some ways to overcome or avoid them. It discusses a multiplication algorithm and multiplicative program. Some computing machine time can be saved if a special multiplication program was written for every AG system. For a trained programmer, this might take less time than doing all the group calculation by hand.