Multigate device

Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.

Abstract: With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-ΦG) and asymmetric (Asymm-ΦG) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-ΦG shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-ΦG SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-ΦG SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-ΦG and Asymm-ΦG FinFETs to optimize leakage, delay, and setup time simultaneously.

Abstract: The junctionless nanowire transistor (JNT) has recently been demonstrated to be a promising device for sub-20-nm nodes. So far, most devices were made on semiconductor-on-insulator substrates. The aim of this work is to evaluate the concept of multigate germanium (Ge) JNTs on bulk substrates, using a dedicated modeling methodology. The variation of device performance due to geometry, channel, and substrate doping concentrations is discussed and proposed as a guideline for designing p-type Ge bulk JNTs. This work shows that a potential barrier is formed in the substrate by the p-n junction that isolates the channel from the substrate, and an effective confinement of current in the nanowire can be achieved. The Ge bulk JNT facilitates excellent scalability. Our modeling predicts that, for a gate length of 16 nm, a subthreshold slope of 77 mV/dec and a drain-induced barrier lowering of 70 mV can be obtained with an $I_{\rm on}/I_{\rm off}$ current ratio of $\hbox{1.1} \times \hbox{10}^{5}$ .

Abstract: The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.