Topic
MULTICUBE
About: MULTICUBE is a research topic. Over the lifetime, 92 publications have been published within this topic receiving 1625 citations.
Papers published on a yearly basis
Papers
17 May 1988
TL;DR: The Wisconsin Multicube, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses and allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi.
Abstract: The Wisconsin Multicube, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data.The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis.The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length.The proposed architecture is an example of a new class of interconnection topologies -- the Multicube -- which consists of N =nk processors, where each processor is connected to k buses and each bus is connected to n processors. The hypercube is a special case where n=2. The Wisconsin Multicube is a two-dimensional Multicube (k=2), where n scales to about 32, resulting in a proposed system of over 1,000 processors.
204 citations
Book•
31 Oct 1998
TL;DR: Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration covers techniques for optimization of system-level memory requirements, and exploration of candidate memory architectures for implementing processor-core-based embedded systems.
Abstract: From the Publisher:
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration covers techniques for optimization of system-level memory requirements, and exploration of candidate memory architectures for implementing processor-core-based embedded systems. It is designed for researchers and graduate students; for designers of embedded systems who are migrating from a traditional micro-controller centered, board-based design methodology to newer design methodologies using IP blocks for process of core-based embedded systems-on-chip; and for CAD tool developers who wish to expand their application base from a hardware synthesis target to embedded systems that combine significant amounts of software and hardware.
173 citations
10 Jun 2002
TL;DR: An analytical method is presented to evaluate embedded network packet processor architectures, and to explore their design space, in contrast to those based on simulation, which tend to be infeasible when the design space is very large.
Abstract: We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.
106 citations
TL;DR: This tutorial gives a structured insight into the field of design space exploration for embedded systems and finds the best compromise between different design goals and their tradeoff.
Abstract: Editor's note :As embedded systems grow more complex and as new applications such as IoT require many design constraints, sophisticated design space exploration techniques are essential in order to find the best compromise between different design goals and their tradeoff. This tutorial gives a structured insight into the field of design space exploration for embedded systems.
80 citations
TL;DR: The embedded robotics mobile robot design and applications with embedded systems 3rd edition that the authors provide for you will be ultimate to give preference.
Abstract: The embedded robotics mobile robot design and applications with embedded systems 3rd edition that we provide for you will be ultimate to give preference. This reading book is your chosen book to accompany you when in your free time, in your lonely. This kind of book can help you to heal the lonely and get or add the inspirations to be more inoperative. Yeah, book as the widow of the world can be very inspiring manners. As here, this book is also created by an inspiring author that can make influences of you to do more.
80 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2019 | 1 |
| 2018 | 1 |
| 2017 | 4 |
| 2016 | 3 |
| 2015 | 5 |
| 2014 | 8 |