Multi-master bus

Abstract: A bus recovery system for multi-master bus system comprises a plurality of bus masters selectively interfacing with a system bus whereby access to the bus is controlled by a bus arbiter. A plurality of counters corresponding to each of the plurality of masters contains a pre-determined time value corresponding to the maximum time each of the plurality of masters may be granted access to bus. The arbiter releases ownership of the bus when the pre-determined time value in the counter has been exceeded by master currently accessing the bus. A register identifies which of the masters had access to the bus when the predetermined time value was exceeded.

Abstract: A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves

Abstract: A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

Abstract: In a system having N devices all using a common data bus (CDB), a priority resolution circuit (PRC) for determining that particular device of the N devices which shall obtain control of the CDB when a device other than the particular device is attempting to obtain control of the CDB and comprising first logic common to all of the devices. A first control bus is common to every device and has a high signal level (SL) thereon when none of the devices is attempting to obtain control of the common data bus and a low SL thereon when any of the devices is attempting to obtain control of the CDB; and a second control bus is common to every device and has a low SL thereon when none of the devices has control of the CDB and a high SL thereon when any of the devices has control of the CDB. Each of the devices, including the particular device, comprises second logic for testing the SL on the first common control bus and responsive to the high SL on the first common control bus to then test the SL on the second common control bus. The second logic of the particular device is further responsive to the low SL of second common control bus to obtain control of the CDB.