Multi-level cell

Abstract: As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput

Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

Abstract: A program voltage signal implemented as a series of increasing program voltage pulses is applied to a set of non- volatile storage elements. Different increment values can be used when programming memory cells to different memory states. A smaller increment value can be used when programming memory cells to lower threshold voltage memory states and a larger increment value used when programming memory cells to higher threshold voltage memory states such as the highest memory state in an implementation. When non-volatile storage elements of a set are programmed to different memory states under simultaneous application of a single program voltage signal, programming can be monitored to determine when lower state programming is complete. The increment value can then be increased to complete programming to the highest memory state. Coarse/fine programming methodology can be incorporated for the highest memory state when the increment value is increased to maintain the threshold distribution within a reasonable range.

Abstract: Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This design's multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.