Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract: The subject matter disclosed herein relates to a photonic module comprising: a plurality of metal pads to receive CMOS integrated circuit (IC) chips to be mounted on a silicon-on-insulator (SOI) wafer; electrical interface circuits to receive electrical signals from the CMOS IC chips and to modify the electrical signals; optical drivers to receive the modified electrical signals and to convert the modified electrical signals to optical signals; and a photonic layer on the SOI wafer comprising silicon optical waveguides and silica optical waveguides to transmit or receive the optical signals for communication among the CMOS IC chips.

Abstract: The invention discloses an RFID (radio frequency identification) reader compatible with a Type A protocol and a Type B protocol, comprising a radio frequency analog front end circuit and a digital baseband circuit, wherein the digital baseband circuit comprises an MCM (multi chip module) control circuit, a Type A coding circuit, a Type B coding circuit, a Type A decoding circuit, a Type B decoding circuit, a first in-first out memory, a first in-first out memory control circuit, a buffer area, a register array, register control, interruption control and a timer. According to the RFID reader compatible with the Type A protocol and the Type B protocol, initial configuration is firstly carried out according to a control command of an external microcontroller, a selected communication mode and operating parameters are written into the register array; then the MCM control circuit obtains the speed and communication protocol adopted by a coding signal transmitted from an RFID label through querying the register array, and a corresponding communication mode is determined; and finally, the radio frequency analog front end circuit transmits various instructions to the RFID label under the determined communication mode and receives an answering signal of the RFID label and data to be read, so that the data to be read can be processed by the external microcontroller.

Abstract: Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6×10.9mm and 8mm×8mm, respectively, are arranged on the interposer through the flip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08×5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.

Abstract: Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

Abstract: Multi-Chip Modules enable combining different integrated circuits with passive components leading to advantages in size, performance and cost. This paper presents the design of a testchip which was planned to extend the characterization of the process parameters for the development of MCM-D technology. It was made using Virtuoso Cadence Software, with minimum dimension of 20 μm, resulting in four mask layers.

Abstract: The utility model provides a multi-chip module light-emitting diode (LED) irradiating treatment device capable of adjusting a spot size. The multi-chip module LED irradiating treatment device comprises a chip integrated LED, a spot adjusting device and a radiating device. The chip integrated LED comprises more than two semi-conductor LED lighting chips and a metal support and is fixed on the radiating device through the metal support, and the spot adjusting device is arranged at the outer end of the chip integrated LED. The multi-chip module LED irradiating treatment device has the advantages of being adjustable in the spot size, large in power density and good in radiating and evenness and solves the problem of a common photon treatment device that the spot size is fixed and can not be adjusted, light pollution is easy to cause, and light condensation is poor.

Abstract: In this paper, a global Chip-Package-PCB Co-Design and Co-Verification methodology is successfully applied to Single-Chip Down-converter circuit and Multi-Chip-Module in transmit mode. Full-wave electromagnetic and thermal Co-Analysis approach is adopted to investigate impact of critical RF couplings, power dissipation and grounding strategies on systemlevel performances. The Single-Chip down-converter circuit shows 43dB conversion gain, with 6.5dB noise figure and output IP3 of 18dBm. The MCM design demonstrates 35dBm output IP3, 25dBm output CP1, with 45dB image rejection with 25dB voltage gain for a dissipated power of 2.2W.

Abstract: This paper presents a multi-chip module (MCM) suitable for GaN monolithic microwave integrated circuit transceivers. The MCM has an embedded heat sink and novel radio frequency interface structure fabricated using multilayer ceramics technology. The novel interface widens the bandwidth and improves insertion loss operating up to millimeter-wave frequencies. A fabricated transceiver MCM occupying only 12 × 36 mm2 is also demonstrated with a GaN power amplifier.

Abstract: Optical multi-chip module enables the integration of high-bandwidth density optical I/Os with high-performance CMOS IC for next-generation high-performance computers by mounting optical and electrical chips directly on waveguide-integrated carrier.

Abstract: The invention discloses a three-dimensional high-density integration method for a thick and thin film multi-chip module. The method comprises the following steps of: firstly, respectively integrating at least one semiconductor chip or chip component on the front face and the reverse face of another small multilayer ceramic substrate, and completing lead bonding of the semiconductor chips; then, enabling all pins externally and electrically connected to be led out from one end face or both faces of a multilayer ceramic substrate; subsequently, respectively forming golden balls in a bonding region of each lead and corresponding bonding regions on the surface of a base multilayer ceramic substrate by adopting a gold ball bonding method or a slurry printing reflow soldering method; and finally, vertically integrating the small multilayer ceramic substrate on the base multilayer ceramic substrate by adopting a eutectic soldering method, an alloy soldering method or a slurry splicing method. According to the three-dimensional high-density integration method for the thick and thin film multi-chip module, by adopting three-dimensional vertical integration, at least one semiconductor chip or other chip components can be vertically integrated on the same base multilayer ceramic substrate, and therefore, high-density three-dimensional integration is realized, and the integration level of the multi-chip module is improved, and the reliability of an application system is improved.

Abstract: The utility model discloses a three-dimensional multi-chip module boards broadband transition structure, which comprises a three-dimensional component module prepared from epoxy resin, an upper circuit board and a lower circuit board which are packaged inside the three-dimensional component module, and a metal layer laid on the surface of the three-dimensional component module. Coplanar waveguide is etched on the metal layer. The upper circuit board is parallelly arranged above the lower circuit board. The coplanar waveguide is vertically arranged on a side of the three-dimensional component module and is perpendicular to the upper and lower circuit boards. According to the structure provided by the utility model, three-dimensional vertical interconnection can be carried out on the 3D-MCM side, and vertical interconnection of multi-layered circuit boards are realized. The interconnection structure occupies no planar circuit area; signal transmission band is wide; insertion loss is little; return loss is also little; the structure is simple; it is easy to expand circuit functions (such as expandable filtering, power distribution and the like) on the side interconnection structure; and registration precision requirements of a vertical circuit and a horizontal circuit are not high. Thus, realizability is technically high.

Abstract: PROBLEM TO BE SOLVED: To realize a multi-chip module which can minimize power consumption during operation by selecting a chip corresponding to throughput without a profiling module mounted.SOLUTION: A multi-chip module has laminated layers of two or more universal LSIs 1, 2 and 3, and a control LSI 4 for controlling operation of the universal LSIs 1, 2 and 3. The control LSI 4 comprises; a power value table 405 for respective universal LSIs having the same function among the universal LSIs 1, 2 and 3; and a selection circuit 404 which refers to the power value table 405 and assigns tasks to one universal LSI which can start among the universal LSIs 1, 2 and 3.

Abstract: PROBLEM TO BE SOLVED: To provide an electronic assembly which is used in a down-hole module and achieves good connection reliability.SOLUTION: An electronic assembly 200 has: a multilayer ceramic assembly; and an electronic component 240 disposed on the multilayer ceramic assembly. The multilayer ceramic assembly includes: a ceramic substrate 220; a nickel plating layer disposed on the ceramic substrate 220; and a gold plating layer disposed on the nickel plating layer and having a thickness of 0.5 micron or smaller. The electronic component 240 is wire-bonded to the gold plating layer by an aluminum wire.

Abstract: The invention relates to a multi-chip module used for control industrial process and a method. The multi-chip module includes a first die having a control processor to generate a signal to control an industrial process and an input/output interface. The multi-chip module also includes a second die having a supervisory processor and an input/output interface. A processor failure of one of the control processor and the supervisory processor is detected by the other of the control processor and the supervisory processor, and the processor that detects the failure is configured to assert a signal through its input/output interface to cause the industrial process to transition to a safe state in response to the failure. Additionally, the first and second dies are created using different process technologies.