Abstract: A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.

Abstract: A semiconductor device in which a plurality of semiconductor chips are stacked. The semiconductor device comprises: a lower side semiconductor chip bonded onto a surface of a wiring substrate; an upper side semiconductor chip; and one or more spacers which are bonded onto the surface of the wiring substrate and which support the upper side semiconductor chip over the lower side semiconductor chip and at a location separated from the lower side semiconductor chip. The upper side semiconductor chip and the lower side semiconductor chip are electrically coupled with the wiring substrate, and whole components on the wiring substrate are encapsulated by an encapsulating resin. The size of the upper side semiconductor chip can be larger than that of the lower side semiconductor chip.

Abstract: In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S() on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S(), and furthermore by having distributed and alternating power supply connections (VCC, GND). The module may comprise two series connected transistors (201, 202) and a control circuit flip chip (300), with bump electrodes (31, 32) and strap connections (181,182) for providing a dc-dc converter without any wire bonds.

Abstract: An integrated module including an array of electrostatically actuated mirrors usable as an optical switch. An array of tiltable mirrors (70, 72) is formed as a micro electromechanical system (MEMS) in one substrate carrier (60). A ceramic multi-chip module (MCM) (62) is formed having multiple layers (80) of wiring and electrodes (94) at one surface forming one side part of the electrostatic capacitive actuators. The MEMS substrate is bonded to the carrier (62) with the carrier electrodes (94) in opposition to the mirrors (70, 72), which form counter electrodes. Advantageously, a handle layer of the MEMS substrate is not removed and the mirrors released until after the bonding with the MCM. Separate high-voltage integrated circuits (ICs) (66) driving the actuators and low-voltage ICs controlling the high-voltage ICs (66) are bonded on the side of the MCM (62) opposite the MEMS (60) with the MCM providing electrical interconnections (68).

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip module suited for a small number of kinds of modules in mass-production. SOLUTION: A circuit block for generating 1.5 V, 1.3 V, and 1.2 V and wirings 26g, 26h, and 26i for feeding these voltages are provided in a large chip 110 on the board side. The three pads 26g, 26h, and 26i are provided for each wiring. Three pads 51g, 51h, and 51i to be connected to a common node Nz are provided on three bare chips IP's 1C, 2C and 3C. The bare chips IP 1C, 2C, and 3C are joined electrically by joining the line between pads 51g and 26g, between pads 51h and 26h, and between pads 51i and 26i to set 1.5 V, 1.3 V, and 1.2 V as the power voltage used. The structure in common for the bare chip IP and the large chip is used as much as possible so that a multi- chip module suited for a small number of kinds of modules in mass production can be provided.

Abstract: The present invention discloses a multi-chip module packaging device which has outward extension portions of under bump metallurgies (UBM) for satisfying the bonding area requirement during wire bonding operation. Therefore, chips have electrical connections with metal bonding wires welded on the extended portions for transmitting electrical signals between each other. That is, the number of circuit layers of the substrate used in the device can be reduced; furthermore save on the production cost.

Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of a multi chip module with respect to a change in temperature. SOLUTION: For example, two integrated circuit chips 24 and 24 are arranged on a substrate 21, with each top face being located in the same plane. Between the integrated circuit chips 24 and 24, a spacer 25 having a coefficient of thermal expansion the same as those of the integrated circuit chips 24 and 24 is located. An interconnection line 26 is formed on the spacer 25 by lithography technology. COPYRIGHT: (C)2004,JPO

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: PROBLEM TO BE SOLVED: To determine quality of interchip connection in semiconductor chips in a multi-chip module, by a simple test circuit and a simple testing method. SOLUTION: A plurality of switch elements 1-31, 1-32, 2-31, 2-32, etc., are arranged to electrify a plurality of connection members 10-1, 10-2, etc., electrically in series, in order to determine the quality the connection between fellow connection pads 1-21 and 2-21, 1-22 and 2-22, etc., between the semiconductor chips 1, 2. When the connection is tested, all the switch elements 1-31, 1-32, 2-31, 2-32, etc., are brought into ON conditions by a probing pad 1-03, and impedances in both ends electrified in series are measured by two probing pads 1-01, 1-02 to determine the quality of the connection between the semiconductor chips 1, 2. COPYRIGHT: (C)2003,JPO

Abstract: PROBLEM TO BE SOLVED: To enable a connection test between chips with a smaller scale circuit in a multi-chip module formed by mounting small chips on a large chip. SOLUTION: A silicon wiring substrate 100 as a large chip is provided with a power source connecting wiring layer 220 formed of power source supply wiring for separately supplying a power source voltage to bare chips IP 10-30 as small chips, a signal wiring layer 230, and connecting pad electrodes 111, etc., connected to each wiring. When testing connecting condition between the pad electrodes 11, etc., of the bare chip IP 10 and the pad electrodes 111, etc., of the silicon wiring substrate 100, a voltage higher than that to be applied to a power source connecting external terminal 119 is applied to a test pad Tp1 provided per each one node of the signal wiring layer 230 to detect intensity of the current or existence of the current, and connecting condition is thereby determined.

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: An automated multi-chip module (MCM) handler for automated module testing which employs a module feed employing a plurality of stackable magazines, the leading one of which in an input stack is positively displaced through an indexing device which positively retrieves each MCM, guides it at a test site, and positively ejects a tested MCM from the test site for sort and direction along an inclined track to either a shipping tray or a discard bin. After a magazine is emptied of MCMs, it continues to an output location where it is stacked with other empty magazines. The test site includes a mechanism for positively engaging and aligning each MCM before engagement by the test contacts. A particularly suitable magazine for use with the handler is also disclosed, as is a method of module handling.

Abstract: An integrated semiconductor circuit ( 10 ) with function inputs ( 14 a ) and function outputs ( 16 a ), as well as with function units ( 12 ), which supply the function outputs ( 16 a ) with output signals which they generate as a function of the input signals applied to the function inputs ( 14 a ), including test inputs ( 18 ) and test outputs ( 20 ), as well as an interface unit ( 22, 26 ) which is inserted between the function units ( 12 ), on the one hand, and some of the function inputs ( 14 a ) and some of the function outputs ( 16 a ). The interface unit ( 22, 26 ) can be switched over, by means of test control signals applied to it, in such a way that it connects these several function inputs ( 14 a ) to the test outputs ( 20 ) or to the function units ( 12 ), and these several function outputs ( 16 a ) to the test inputs ( 18 ) or to the function units ( 12 ). A multi-chip module can be assembled on a common substrate ( 30 ) from a plurality of such integrated semiconductor circuits ( 10, 32 ), whereby the interface units of the semiconductor circuits contained in the multichip module make it possible to check these individual semiconductor circuits.

Abstract: The present invention discloses a multi-chip module packaging device which has outward extension portions of under bump metallurgies (UBM) for satisfying the bonding area requirement during wire bonding operation. Therefore, chips have electrical connections with metal bonding wires welded on the extended portions for transmitting electrical signals between each other. That is, the number of circuit layers of the substrate used in the device can be reduced; furthermore save on the production cost.

Abstract: Techniques to obtain a high isolation property in a multi-chip module (MCM) between pads of a SiGe-MMIC flip-chipped on a low temperature co-fired ceramic (LTCC) are discussed. In such an MCM, there are two coupling paths. One is a path through the LTCC and the other is a path through the MMIC. To improve the total isolation property, structures to reduce the two coupling paths are required because the paths of such leakage are not in series but in parallel. We examined the disposition of several kinds of ground patterns on the LTCC. Also, we devised a metal plate on a bias circuit as a shielding structure on the SiGe-MMIC. The effectiveness of the isolating structures was verified by measuring IIP2 in a receiver MCM with a direct conversion SiGe-MMIC. The IIP2 property has been improved successfully as well as the isolation property.

Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Abstract: PROBLEM TO BE SOLVED: To solve the problem that conventional multi-chip module joining method couldn't keep levelness of a common electrode because of a tilt or the like of each semiconductor chip which is jointed to the substrate. SOLUTION: First, a common electrode 40 is jointed through each of solders 22 and 32, with the semiconductor chips 20 and 30 placed at the predetermined position on a smooth standard surface A-A'. Next, the semiconductor chips 20 and 30 which are jointed to the common electrode 40 are jointed on the substrate through the solders. By doing so, the levelness of the common electrode 40 can be maintained, and the jointing intensity of a wire which is wire- bonded on the bonding surface of the common electrode 40 can be stabilized. COPYRIGHT: (C)2003,JPO

Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.

Abstract: The present invention provides a flexible combination slot which is used to connect plurality of crystals with a programmable multi-chip module consisting of plurality of field programmable interconnect chips. The flexible combination slot is connected by at least one field programmable interconnect chip with one of weld pads of the programmable multi-chip module and consists of plurality of the first slot modules which can selectively place and connect at least one crystal. The routing of the plurality of crystals and the routing between the crystal and the weld pad is finished by the RW field programmable interconnect chip so that an universal quick configurated and easy to detect error substrate can be provided for the User by utilizing the programmable multi-chip module configurated by the flexible combination slots of present invention.

Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

Abstract: Two integrated circuit chips, for instance, are disposed on a substrate such that the top surfaces of these integrated circuit chips are located within the same plane surface. A spacer having substantially the same coefficient of thermal expansion as the one of the integrated circuit chips is disposed between the integrated circuit chips. Wiring is formed on the spacer by means of lithography technology.