Abstract: There is provided a flexible package which includes a flexible substrate on a principal surface of which a plurality of metal wirings are formed, a flexible semiconductor chip attached over the flexible substrate and having a plurality of bonding pads thereon, joint metals for connecting electrically the plurality of bonding pads and the plurality of metal wirings respectively, and a sealing member sandwiched between the flexible substrate and the flexible semiconductor chip. The flexible semiconductor chip in which thickness of the semiconductor chip is reduced smaller than the normally-used thickness to lower the rigidity is mounted. Also, the rigidity of the overall package is made smaller by reducing thicknesses of respective constituent parts of the package such as the flexible substrate, etc. Therefore, generation of the package crack due to displacement can be avoided. In addition, since the sealing member is sandwiched between the flexible substrate and the flexible semiconductor chip, the warpage of the package can be suppressed extremely small. Therefore, flatness of the flexible package as a single product can be assured sufficiently. Further, if a packaging substrate on a principal surface of which a plurality of packaging wirings are formed is prepared and then the plurality of packaging wirings are connected electrically to the plurality of metal wirings respectively, the module with high packaging reliability can be constructed. Moreover, if a plurality of flexible packages are laminated, a MCM having a small total thickness can be constructed.

Abstract: A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, "semiconductor elements") may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond. The present invention also includes a stacked configuration. After attachment of semiconductor elements, the carrier substrates can be stacked to form a high density stacked configuration.

Abstract: A compact multi-chip module is provided. The multi-chip module may be built from a lead frame that does not have a die attach pad. Instead, the leads of the lead frame may define a central opening. A first semiconductor device extends across the central opening and is connected to the plurality of leads, with the leads being on a first side of the first semiconductor device. A second semiconductor is stacked on the first side of the first semiconductor device. A third semiconductor device is stacked on the second semiconductor device. A fourth semiconductor device is stacked on the third semiconductor device. The stack of semiconductor devices passes through the central opening formed by the plurality of leads. The stack of semiconductor devices is encapsulated with a thermoset plastic. The resulting final assembly may occupy no more volume than a typical single chip component.

Abstract: A test module for simultaneously testing a plurality of IC packages in a simulated multi-chip module environment. The test module includes a module board adapted to receive the IC packages and a plurality of module adapters configured to secure the IC packages to the module board. The module adapters secure the IC packages to the module board and establish electrical contact between the IC package leads and a plurality of contact pads disposed on the module board, with no permanent bonding agent. Reliable electrical connections are established between the IC package leads and the contact pads by a plurality of protruding pins extending from each module adapter, which bias the IC package leads towards the contact pads. A plurality of IC packages assembled into the test module may be subjected to module level testing. During any stage of module level testing, any of the IC packages may be easily removed from the test module without the attendant damage resulting from severing of permanent electrical bonds ordinarily formed between the IC package leads and a conventional multi-chip module substrate. If the IC packages assembled into the test module exhibit specified operational characteristics during module level testing, the IC packages may be removed from the test module without damage and permanently assembled into a multi-chip module.

Abstract: A multi-chip module includes metal frame segments including a plurality of die-bonding pads and a plurality of terminals, a plurality of electronic components mounted on the die-bonding pads in electrical connection to the terminals, and a resin package for enclosing the electronic components and the metal frame segments with each of the terminals partially projecting outwardly from the resin package. Selected ones of the electronic components are electrically connected to each other via the metal frame segments and wires within the resin package.

Abstract: High power density within very small regions is a typical feature of advanced millimeter wave devices and components. Sufficient cooling has to be guaranteed during operation also under unfavorable ambient conditions. In the research project "Multifunctional Micro- and Millimeterwave Modules (4M)", funded by the BMBF of Germany, a 28 GHz communication unit was developed using low temperature cofired ceramic (LTCC) multi layer substrates as a basis for the millimeter-wave multi chip module (MCM). The TX and LO signal amplifier GaAs chips produce a major part of the dissipated power that has to be transferred to the base plate of the system. Thermal vias were implemented into the LTCC multilayer in order to overcome the poor thermal conductivity of the substrate material. The via diameter and pitch as well as the different possibilities of die assembly had to be optimised with regard to thermal and cost aspects. The authors explain their approach in thermal via and die assembly optimisation. It will be described how the best suited thermal via arrangement was found by means of finite element (FE) submodeling, which enabled a very detailed thermal analysis for a wide variety of thermal via arrangements. Two assembly technologies, soldering and gluing, were studied in order to characterise the thermal resistances of the different layers between die and case. The heat sharing of the several paths could be quantified. An optimised assembly process could be proposed which ensures sufficient cooling and minimum Ag or AgPd volume. The comparison of calculated and measured surface temperatures allows for the influence of inaccurate parameters in the FE model to be diminished and leads to a more realistic FE modeling of prospective electronic assemblies.

Abstract: Disclosed is a multi-layered multi-chip module which comprises a substrate, a first electric shield line formed on the substrate, a passive element layer having passive elements and being formed on the first electric shield line, a second electric shield line formed on the passive element layer, an interconnection layer having a connection line electrically connected to the passive elements and being formed on the second electric shield line, a third electric shield line formed on the interconnection layer, a plurality of bumpers electrically connected to the connection line and formed on the outside of the third electric shield line, and a plurality of integrated circuits (IC) or electrical elements formed on the bumper. According to the present invention, the base band unit and the RF unit can be formed into a single module, and the size of the module can be reduced since the ICs and the passive elements are provided in the different layers.

Abstract: An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

Abstract: We have developed a thick film multi-chip module for readout of silicon drift (or low capacitance ∼200 fF) detectors. Main elements of the module include a custom 16-channel NPN-BJT preamplifier-shaper (PASA) and a custom 16-channel CMOS Switched Capacitor Array (SCA). The primary design criteria of the module were the minimizations of the power (12 mW/channel), noise (ENC=490 e − rms), size (20.5 mm×63 mm), and radiation length (1.4%). We will discuss various aspects of the PASA design, with emphasis on the preamplifier feedback network. The SCA is a modification of an integrated circuit that has been previously described [1]; its design features specific to its application in the SVT (Silicon Vertex Tracker in the STAR experiment at RHIC) will be discussed. The 240-channel multi-chip module is a circuit with five metal layers fabricated in thick film technology on a beryllia substrate and contains 35 custom and commercial integrated circuits. It has been recently integrated with silicon drift detectors in both a prototype system assembly for the SVT and a silicon drift array for the E896 experiment at the Alternating Gradient Synchrotron at the Brookhaven National Laboratory. We will discuss features of the module's design and fabrication, report the test results, and emphasize its performance both on the bench and under experimental conditions.

Abstract: Many different sensor types and their associated electronic systems are utilized for aircraft and aerospace applications. When atmospheric data is collected like pressure load surveys for aircraft, arrays of many sensors are required on a common bus. With the support from a device manufacturer, we have been developing a multi-Micro-Electro-Mechanical System (MEMS) sensor based electronic system. We report in this paper a unique electronic packaging configuration incorporating MEMS sensors, multi-chip modules (MCMs) and tape automated bonding (TAB) carrier. Electronic assembly and interconnection methods used for various levels of packaging are also described. They include direct-chip-attachment (flip chip) process for the MEMS device to the module and bus connection through TAB carrier to the host computer. Encapsulation material for electronic components was selected for improving the reliability of the module. Localized circuit functionality was needed to conduct temperature compensation and self-calibration. A thin and/or miniaturized profile was required for aerodynamic reasons. Fully assembled hardware in the form of a pressure belt was installed on airplanes and passed two separate flight tests. Data analyses on these flight test results are also included.

Abstract: A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.

Abstract: A method of packaging a multi chip module (MCM) with low cost and high reliability is disclosed. In the MCM process, a plurality of bare chips and CPSs, such as CPU or memory device, are integrated on a substrate to increase the package density. The method discards the high cost KGD process and directly takes the thin and small CSPs passing the tests as KGD and integrates the chips and CSPs into ball grid array package (BGA package) so that the cost is reduced and the yield and quality of the package is improved.

Abstract: A multi-chip module (MCM) based on High Density Interconnect (HDI) technology was developed for the front-end electronics of a high energy nuclear physics experiment to process charge pulses from silicon detectors. Stringent requirements in performance as well as low radiation length and minimum physical size of the module dictated the use of the most sophisticated MCM technology available. The module handles 256 input channels on an alumina substrate with milled cavities for die placements and four layers of thin-film traces of 42u width. A total of 20 custom integrated circuit chips and 98 passive components are assembled on a substrate of size 43 mm/spl times/48 mm. Various aspects of development efforts for the design and fabrication as well as the electrical test results of the module are discussed.

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip module semiconductor device for achieving a high-speed switching operation by reducing the wiring inductance and wiring resistance between the voltage drive transistors of a plurality of semiconductor elements, and matching the switching operation timing of each voltage drive transistor. SOLUTION: A multi-chip module semiconductor device is provided with an emitter power supply plate 6 that is common to emitter electrode terminals 511 and 521 of each of a plurality of semiconductor elements 51 and 52. The emitter power supply plate 6 is formed, for example, by a Cu plate. An opening 61 for connecting gate is provided at the central part of the emitter power supply plate 6, and gate electrode terminals 510 and 520 of the semiconductor elements 51 and 52 are provided in the opening 61 for connecting gate.

Abstract: PROBLEM TO BE SOLVED: To realize high density mounting of an electronic component by building thin electronic components onto an external conductor circuit of a multi- layer printed wiring board and also into an internal conductor circuit thereof and connecting them together. SOLUTION: In a multi-module 100, many electronic components 14, 15 and 16 are mounted on a multi-layer printed wiring board 10, the electronic component 15 is mounted on an external conductor circuit 11 of the board 10, the thin electronic components 14 and 16 are mounted between internal insulating layers 12 of the board 10 and electrically connected to the internal conductor circuit 13. The internal insulating layer is provided with a recess or opening 17 for accommodation of the thin electronic components 14 and 16, and a gap between the recess or opening 17 and the thin parts 14 and 16 is filled with prepreg adhesive of the board 10. COPYRIGHT: (C)2001,JPO

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip module which can be removed easily from a circuit board. SOLUTION: A multi-chip module 1 or electronic semiconductor element has a multilayered substrate 9, and the bottom face of the bottom layer 15 of the substrate 9 works as a bonding surface when the module 1 or element is bonded to a printed wiring board with a heat-sensitive adhesive, solder, etc. The bottom layer 15 of the substrate 9 of the module 1 is integrally provided with a plurality of electric heaters arranged in parallel. When the heaters are energized with appropriate currents, the heaters generate heat sufficient to weaken the bonded joints of the adhesive and makes the peeling or removal of the module 1 or element from the printed wiring board easier without weakening the bonded joints from among many layers in the laminated substrate 9 nor the bonded joint of the module 1 or element to the substrate 9.

Abstract: A multiple semiconductor chip module for use in high-power applications includes at least a power semiconductor chip (30) and a control semiconductor chip (40) mounted on an electrically conductive heat sink (20). The power semiconductor chip may be a Silicon-On-Insulator (SOI) device and the control semiconductor chip may be a semiconductor device having a substrate connected to ground potential. The power semiconductor chip and the control semiconductor chip are directly mounted on the electrically conductive heat sink without the use of a separate electrical insulation layer in order to obtain a multi-chip module which is simple and economical to manufacture, and which offers superior performance characteristics.

Abstract: Disclosed is a multi-layered multi-chip module which comprises a substrate, a first electric shield line formed on the substrate, a passive element layer having passive elements and being formed on the first electric shield line, a second electric shield line formed on the passive element layer, an interconnection layer having a connection line electrically connected to the passive elements and being formed on the second electric shield line, a third electric shield line formed on the interconnection layer, a plurality of bumpers electrically connected to the connection line and formed on the outside of the third electric shield line, and a plurality of integrated circuits (IC) or electrical elements formed on the bumper According to the present invention, the base band unit and the RF unit can be formed into a single module, and the size of the module can be reduced since the ICs and the passive elements are provided in the different layers

Abstract: This paper focuses on the issues concerning the system design of an IC implementation of a new integrated sensor and signal conditioning module for automotive anti-locking brake systems (ABS). It describes a concise solution for the detection of the speed and direction of rotation of a car-wheel. The signal conditioning is realised by digital control of analog elements and a new signalling protocol is detailed which transmits information via modulation of the supply current. The system functions in a harsh operating environment to above 150°C, with the external supply voltage varying from 40 V to 4.5 V, and features robust EMC performance. It is realised as a Multi Chip Module (MCM) in BiCMOS/DMOS (BCD) and CMOS processes, and is completely contained in a two pin package with no external components. (6 pages)

Abstract: PROBLEM TO BE SOLVED: To provide a base for a multi-chip module with low cost and simple handling and method of producing a multi-chip module using the same SOLUTION: A base for a multi-chip module in which an electrical circuit for mounting a plurality of semiconductor elements and electrical/electronic components are formed thereon In this case, the base is one formed with an electrical circuit 4 coated by electroless plating the surface of a plastic molding 3a and the inner surface of a through-hole 2, the plastic molding 3a in which a recess 1 is formed thereon, and plural through-holes 2 are formed surrounding the recess 1

Abstract: The invention relates to a multi-chip module and a method for producing the same. The inventive module has a base substrate on a part of which signal conductor tracks and signal contact surfaces are arranged in at least one layer. The module further comprises a semiconductor component that is linked with signal conductor tracks and signal contact surfaces and that works in the signal range. The aim of the invention is to provide a highly integrated multi-chip module. To this end, power conductor tracks and power contact surfaces are arranged at least on part of the base support and in at least one layer. At least one power electronic component is provided that works in the power range and that is linked with a power conductor track, at least one power contact surface and at least one signal conductor track. The power conductor tracks have a larger diameter than the signal conductor tracks at least due to a higher thickness.

Abstract: The explosion of global mobile telephone market has resulted in strong need for wide range and variety of packaging technologies in order to supply personal phones with enhanced product miniaturization, cost reduction, and good electrical performance. In that regard, Multi-Chip Module (MCM) is inevitably the one of the choice for the packaging of the mobile telephone. In this paper, we introduce an RF MCM-L transceiver module packaged by BGA for a 1.8-GHz personal communication service (PCS). We have focused most of our effort on low-cost and high-density design for the module. Basically, the low cost design is achieved using MCM-L substrate. The miniaturization of the transceiver was accomplished using optimally unified decoupling capacitors, thin MCM-L substrate and bare-chip mount technology. The second level package type of the RF MCM-L transceiver is ball grid array (BGA) with the ball size of 400 /spl mu/m. HP ADS and Maxwell software are used for the circuit and the interconnection simulation, and HP 8595E-spectrum analyzer is used for the RF measurement. The total area of the RF MCM transceiver is only 2.25 cm/sup 2/ which is reduced by 37.5% compared to the hybrid package type. The receiver of the RF MCM transceiver has exhibited typical 8 dB gain and 2.5 dB noise figure (NF). 1-dB saturation point is over -9 dBm. The transmitter of the RF MCM transceiver has had shown the typical gain of 25 dB. The power consumption of the receiver and the transmitter are 180 mW and 416 mW, respectively.

Abstract: PROBLEM TO BE SOLVED: To reliably execute tests on a semiconductor device as a single body before it is assembled to a multi-chip module on the semiconductor device and the multi-chip module on which a plurality of the semiconductor devices are mixed by mounted. SOLUTION: A semiconductor memory device is connected to an interface part of the semiconductor device. A built-in memory formed in the semiconductor device is connected to at least part of the interface part. A memory selecting circuit makes the built-in memory accessible at a first operation mode and makes the built-in memory inaccessible at a second operation mode. For example, by placing the semiconductor device in the first operation mode and accessing the built-in memory, it is possible to make the semiconductor device operate as a predetermined system even when a semiconductor memory device is not connected to the interface part. By using the built-in memory instead of the semiconductor memory device it is possible to test the interface part and circuits related to the same with the semiconductor device as a single body. COPYRIGHT: (C)2002,JPO

Abstract: PURPOSE: A multi chip module is to increase its capacity and reduce a mounting surface by mounting many semiconductor chips on a ceramic substrate and to maximize heat dissipating effect by providing many heat sinks and caps CONSTITUTION: A ceramic substrate(10) includes a circuit pattern and many slots thereon At least two semiconductor chips have one side mounted on and fixed to the ceramic substrate and a bonding pad(22) on that side A heat sink(30) is provided between adjacent semiconductor chips to dissipate heat generated from the semiconductor chip to exterior The circuit pattern is arranged at one side wall of the slot opposite to top surface of the semiconductor chip The chip is attached to the slot provided on the ceramic substrate by an insulating adhesive(50) The bonding pad is arranged in a row at a part of the semiconductor chip arranged within the slot A solder bump is formed on the bonding pad The semiconductor chip is electrically connected to the circuit pattern through an anisotropic conductive film therebetween

Abstract: The invention relates to a multi-chip module for LOC assembly, whereby several semiconductor chips which are located on a wafer before the LOC assembly are arranged next to each other in a connecting frame. The invention also relates to a method for producing said multi-chip module. In order to keep the number of malfunctions during assembly as low as possible and to reduce the assembly time in relation to conventional assembly methods, the invention proposes to arrange part or all of the semiconductor chips located in the connecting frame on a common, continuous section of the wafer, even after the LOC assembly of the module. To achieve this, the desired arrangement of chips in the connecting frame is already obtained on the wafer and the section of wafer containing this arrangement is subsequently separated as a common, continuous section and is placed in the connecting frame.

Abstract: Simultaneous communication with multiple subscribers is achieved in certain base stations topologies by utilizing several receive chain sections for each of the antennas. Due to the large number of receive modules in such topologies, modules must be low cost and small size. On the other hand, base stations receive line-ups, are very demanding on dynamic range. While for the subscribers end, the performance versus cost optimization often ends up with multifunction MMICs, the optimization for higher performance required for base stations leads to circuits, based on discrete components or on MMICs of different technologies. A multi chip module based on MMICs with embedded elements, is a small, low cost, and low part count solution, which maintains high performance. The described work includes the design of two GaAs MMICs and RF circuitry, and their integration with GaAs and silicon discrete chips into a MMCM.