Abstract: A cooling structure for a multi-chip module includes a multi-chip module, a fan-builtin heat sink, a cooling fan, and openings. In the multi-chip module, a plurality of chips are mounted on a wiring board. The heat sink has a bottom plate and is arranged above the multi-chip module. The cooling fan is arranged in an upper portion of the heat sink to cool the multi-chip module. The openings are formed in a bottom plate of the heat sink to supply air from the cooling fan to the multi-chip module.

Abstract: A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.

Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.

Abstract: A method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results is accomplished by a multi-chip module that includes a first circuit disposed on a first chip substrate, a second circuit disposed on second chip substrate, and an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate. The interconnecting substrate connects the first circuit to the second circuit. The interconnecting substrate includes external connectors for accessing signals within the multi-chip module, which allow the multi-chip module to be fully tested. This testing may include isolating the first circuit and/or the second circuit by disabling other circuits in order to allow each of the circuits to be exercised without interference from other circuits. After testing the multi-chip module, configuration circuitry included on the multi-chip module may be used to reconfigure the multi-chip module based on results of the testing.

Abstract: An improved multi chip module (MCM) and a method for forming the multi chip module are provided. The multi chip module includes a semiconductor wafer and an interconnect substrate having contact members adapted to establish electrical communication with dice contained on the wafer. The contact members can be formed as etched pillars with penetrating projections or as microbumps on a flexible tape. An alignment plate associated with the interconnect substrate includes an alignment opening adapted to mechanically align bond pads, or other contact locations, on the wafer with the contact members on the interconnect substrate. The multi chip module also includes a force applying member in the form of a compressible bladder or elastomeric member, adapted to press the wafer against the interconnect substrate. In an alternate embodiment, the multi chip module includes tested singulated dice and the alignment plate includes multiple alignment openings.

Abstract: A multi-chip module (“MCM”) and methods of operation and manufacture thereof The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip

Abstract: A reworkable cold welded microelectronic multi-chip module contains cold welded microelectronic chips in which the chip's cold weld metal bonding pads (3) are constructed of a metal having one hardness and the corresponding cold weld metal bonding pads of the multi-chip module's substrate (5) are of a different greater hardness, which, despite the difference in hardness, cold weld to one another. Two forms of Indium preferably serve as the metals. If for any reason the chip must be removed from the module, it is found that the cold weld breaks at a predictable location. A new microelectronic chip may thereby be cold welded to the module substrate as a replacement. New rework and testing procedures are thereby made possible.

Abstract: The steady state thermal performance of semiconductor packages has been traditionally reported through the use of a single junction-to-ambient thermal resistance constant commonly referred to as /spl theta//sub ja/. This is particularly inadequate for multi-chip modules, where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multi-chip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit.

Abstract: An automated multi-chip module (MCM) handler for automated module testing which employs a module feed employing a plurality of stackable magazines, the leading one of which in an input stack is positively displaced through an indexing device which positively retrieves each MCM, guides it at a test site, and positively ejects a tested MCM from the test site for sort and direction along an inclined track to either a shipping tray or a discard bin After a magazine is emptied of MCMs, it continues to an output location where it is stacked with other empty magazines The test site includes a mechanism for positively engaging and aligning each MCM before engagement by the test contacts

Abstract: For the ATLAS experiment at the planned Large Hadron Collider (LHC) at CERN hybrid pixel detectors are being built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the ATLAS pixel detector. A module consists of a sensor tile with an active area of 16.4 mm/spl times/60.4 mm, 16 read out ICs, each serving 24/spl times/160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and power distribution busses. The dies are attached by flip-chip assembly to the sensor diodes and the local busses. In the following a module based on MCM-D technology will be discussed and prototype results will be presented.

Abstract: PROBLEM TO BE SOLVED: To enable ICs to be integrated into a multi-chip module by a method wherein a first chip is equipped with a first and a second circuit part which are connected together with a signal conductor, the first and second chip are connected direct together with the signal conductor of the first chip, and the second circuit part of the first chip is bypassed. SOLUTION: ICs 111 and 121 are equipped with signal processing circuits 112 and 122 (first circuit part) respectively, and furthermore the ICs 111 and 121 are provided with conductor IC buses 113 and 123 respectively so as to store data in common. Moreover, the ICs 111 and 121 are provided with a serial input/output port (second circuit part) connected to the IC buses 113 and 123 respectively. At this point, a multi-chip module 200 is furthermore equipped with a lead 230 (mutual connecting means) which connects the IC bus 113 of the IC 111 to the IC bus 123 of the IC 121. By this setup, the buffers of a multiplex circuit and the ICs 111 and 121 can be bypassed.

Abstract: This paper proposes a novel silicon-on-silicon multichip module with an integrated thermal management system. Our module offers a new packaging approach, which allows great densification of the number of electronic circuits on a common substrate that is almost equivalent to wafer scale integration, yet uses discrete chips. Wet anisotropic etching is used for the separation of silicon integrated circuits as well as for the fabrication of the chip-receiving cavities in the MCM substrate. The etching exposes Si{111} planes in both chip and receiving surface, assuring a virtually perfect mating of the assemblage. The system is complemented with an integrated cooling channel which allows the removal of heat fluxes up to 300 Wcm/sup -2/.

Abstract: PROBLEM TO BE SOLVED: To provide a reliable mounting structure of a semiconductor multi-chip module which can efficiently radiate a large quantity of heat generated from the module based only on heat conduction. SOLUTION: In the mounting structure of a multi-chip module, a heat conductive sheet 4 applied onto a rear side of a chip size package(CSP) 1 is contacted with a metallic radiator 3, metallic radiator plates 9 are inserted into heat- diffusing grooves 12 made in the metallic radiator 3, and then screwed to metallic radiating poles 5 erected on a CSP-mounting side of a printed circuit board 8. A copper foil pattern 6a is thermally coupled with another copper foil pattern 6b on the other surface of the board 8 through through-holes 7 of the board 8. The pushing pressure of the radiator 3 and conductive sheet 4 can be adjusted freely by means of spacers 10 provided to the poles 5. Thus the generation of a thermal/mechanical pulling stresses with respect to metallic bumps between the CSP 1 and CSP mounting board 2 can be prevented beforehand.

Abstract: PROBLEM TO BE SOLVED: To attain laminated high density by using a generally used semiconductor chip as it is at the time of constituting a multi-chip module. SOLUTION: This high density multi-chip module is provided with semiconductor chips 1 and 2 integrated by joining the mutual non-circuit faces, and a sub-substrate 5 electrically/mechanically connected with an MCM substrate 3. One semiconductor chip 1 of the integrated semiconductor chips 1 and 2 is flip-chip connected with the MCM substrate 3, and the other semiconductor chip 2 is connected by bonding with the sub-substrate 5. COPYRIGHT: (C)1999,JPO

Abstract: PROBLEM TO BE SOLVED: To perform the protection of a semiconductor bare chip without fail, and enable the improvement of assembly efficiency, and validate high-density mounting by covering a bump mounting hole, and also arranging a semiconductor bare chip in the specified position of a circuit board face, and jointing a metallic pattern with the conductor pattern of the circuit board SOLUTION: This multi-chip module is provided with a circular bump mounting hole 18 by hollowing out the section corresponding to an electrode 7, when overlaid on the electrode face of a semiconductor bare chip 6 Then, only the electrode 7 is exposed when a heat-resistant insulating film 17 is put on the electrode face of a semiconductor bare chip 6 A metallic bump 8 is jointed in solid phase to the electrode 7, bringing a wire-bonding method into practice, with this heat-resistant insulating film 17 on the electrode face of the semiconductor bare chip 6 Furthermore, the metallic bump 8 and the heat-resistant insulating film 17 are attached to all the semiconductor bare chips 6, and the metallic pattern 8 of the semiconductor bare chip 6 is jointed to the conductor pattern 12 of a circuit board 11, with the face where only the metallic bump 8 is exposed, directed towards the circuit board 11

Abstract: A quantitative analysis of thick film chip resistors is presented in this work regarding design and construction. Critical rel iability and performance data are compared for two techniques used to adjust final resistance tolerance; abrasive trimming and laser trimmin g. Additional enhanced performance characteristics are discussed for diamond sawing versus laser scribing methods of die separation, a nd three-sided versus five-sided surface mount terminations, including nickel barrier and solderability aspects. This analysis will provide v ital information for component engineers working with parts specifications for thick film passive components. Additionally, specification guidelines are defined based upon each given packaging and electrical application for optimum perfo rmance and reliability of a thick film passive component. These guidelines are specified for applications involving epoxy die attach, eut ectic die attach, wirebonding, and surface mount reflow soldering. Some typical pitfalls that occur using an incorrectly specified component for a given application are discussed in this work.

Abstract: PROBLEM TO BE SOLVED: To provide the integrated circuit device, its connecting method, and the multi-chip module which make it possible to easily interconnect integrated circuit devices, suppress variance in wiring length, and can constitute a stable, high-performance multiprocessor device. SOLUTION: Processor elements 1.1-1.n are connected in an L shape by inter- processor communication buses 2.1.1-1.2m.4m-1 to constitute 2m processor groups. The 2m processor groups 3.1-3.2m are arranged on one processor chip. Further, identical processor chips are arranged on the multi-processor module while changed in direction, and the adjacent processor chips are connected by the communication buses. At both the ends are, input/output terminals on the same processor chip are folded and connected. Consequently, a unidirectional ring bus multiprocessor system is constituted which has all the processor elements connected in a ring shape.

Abstract: The amount of electronic equipment loaded in cars is increasing. All parts of the vehicle are now driven by electronics, such as the engine control unit which manages the engine, or clutch and gear box systems which manage the car chassis, or, more recently, the alarm and navigation systems which manage the car body. Each generation of electronic equipment must be increasingly powerful, but at the same time the size must be reduced. Higher clock rates and data exchanges are good solutions for increased electronic equipment performance, but are bad for electromagnetic radiation. The use of multichip modules, with dice directly bonded to a small PCB, mixes the advantages of reduced hardware size for equivalent performance, a single package for several dice, and also to reduce the radiated electromagnetic field. This paper presents the differences in radiated emission levels between a microcontroller alone and a MCM using the same microcontroller with RAM and flash memory. The methodology used for the comparison according the American SAE 1752/3 standard is described. The test method used a TEM cell specially designed for component emission tests in the 150 kHz to 1000 MHz range. An analysis of the results allows identification of the different noise origins, such as the device core, clock systems and bus distribution. This also allows quantification of the gain of around 10 dB on radiated emission levels up to 1 GHz.

Abstract: The semiconductor element has several stacked substrate layers (2,3,2a,3a,2c) and several semiconductor chips (1) with flip-chip contacts (12) and contact pads (7) connected to the element contacts (17) via conductor paths (4). The substrate layers are selectively provided with openings (14) for locating the semiconductor chips and the conductor paths for connecting the chips to the element contacts, each extending from the chip to the edge of the substrate layer.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip module having a high processing speed with few signal layers. SOLUTION: The module comprises an MCM structure 1, having surface layer wiring patterns 7, inner layer wiring patterns 8, a chip-mounting parts at specified areas of the surface, and pads 2 connected to the wiring patterns 7, 8 round the chip mounting areas, bare chips LSI 3a, 3b which are mounted on the chip-mounting areas on the substrate 1 and have pads 4a, 4b on the surface, bonding wires 6 which connect the pads 4a, 4b mutually between the chips LSI 3a, 3b, connected to the adjacent chip-mounting parts on the substrate 1, and bonding wires 5 which connect predetermined pads 2 on the substrate 1 to the pads 4a, 4b on the chips LSI 3a, 3b.

Abstract: A 2.5-Gbit/s 22-kGate SDH termination circuit has been developed that uses a power-management technique and has a multi-chip module design. Size and power are reduced to 1/10 and 1/6 that of currently available modules.

Abstract: This paper describes the modeling approach and numerical results of MCM transmission lines formed by interwoven metallization patterns. The impedance of the signal traces is calculated based on quasistatic field approximations. The differences between conventional microstrip and interwoven transmission lines are pointed out and ample data are provided for the "weaved" line as a function of several geometrical parameters.

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip module for preventing ringing from increasing owing to the increase and reflection of wiring delay by suppressing the increase in size of a substrate size and the extension of wiring length. SOLUTION: A bare chip IC1 is mounted to a multilayer board 3 and is electrically connected to a multilayer board 3 and a bare chip IC1 by a wire 2. I/O terminals 5a and 5b supply signals, power supplies, or ground to the multilayer board 3 and an I/O terminal connection pad 6 is provided between the multilayer board 3 and the I/O terminals 5a and 5b. The I/O terminals 5a and 5b are also connected to a multilayer board 7 for converting the number of I/O terminals. The multilayer board 3 and an I/O pad 19 provided on the multilayer board 7 for converting the number of I/O terminals are connected. In this manner, signals in the multilayer board 3 and the multilayer board 7 for converting the number of I/O terminals are connected at both the I/O terminals 5a and 5b and the conductor 8 of a flexible board.

Abstract: The circuit is formed in the micro-hybrid technique, or as a multi-chip module (MCM), or as chip on board (COB) and contains a processor (3) on a circuit board (1). To the processor are coupled signal lines (4-6) into which are fitted series resistors to improve its electromagnetic compatibility (EMV). The series resistors are in the form as paste filled conductive ducts (9-11) in the circuit board as components of the signal lines. Alternatively, the connection of the processor and circuit board is carried out by bond wires, whose material, thickness and length determines the series resistors.