Showing papers on "MOSFET published in 2015"
TL;DR: This paper demonstrates band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on and is the only planar architecture tunnel-fET to achieve subthermionic subthreshold swing over four decades of drain current, and is also the only tunnel- FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts.
Abstract: A new type of device, the band-to-band tunnel transistor, which has atomically thin molybdenum disulfide as the active channel, operates in a fundamentally different way from a conventional silicon (MOSFET) transistor; it has turn-on characteristics and low-power operation that are better than those of state-of-the-art MOSFETs or any tunnelling transistor reported so far. Traditional transistor technology is fast approaching its fundamental limits, and two-dimensional semiconducting materials such as molybdenum disulfide (MoS2) are seen as possible replacements for silicon in a next generation of high-density, lower-power chip electronics. A particularly promising prospect is their potential in band-to-band tunnel transistors, which operate in a fundamentally different way from conventional silicon (MOSFET) transistors. So far, few such devices with overall characteristics better than silicon transistors have been demonstrated. Now Kaustav Banerjee et al. have built a tunnel transistor by making a vertical structure with atomically thin MoS2 as the active channel and germanium as the source electrode. It has turn-on characteristics and low-power operation that are better than those of existing silicon transistors, and the results will be of interest in a range of electronic applications including low-power integrated circuits, as well as ultra-sensitive bio sensors or gas sensors. The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal–oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor’s gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials1,2,3,4,5,6,7 have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing8,9. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling10,11,12,13,14,15,16. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors18,19,20,21.
951 citations
TL;DR: In this paper, the authors investigated the reliability issues of the SiC MOSFET gate oxide under standard short-circuit test conditions, and also their shortcircuit sustainability (tolerance) have been studied at different drain-source and gate-source voltages.
Abstract: Silicon-Carbide (SiC) MOSFETs, due to material properties, are designed with smaller thickness in the gate oxide and a higher electric field compared to Si MOSFETs. Consequently, the SiC MOSFETs have a worse reliability which causes higher leakage currents during instantaneous abnormal operating conditions. This paper investigates the reliability issues of the SiC MOSFET gate oxide under standard short-circuit test conditions. In this paper, 1200-V SiC MOSFETs are newly modeled, and also their short-circuit sustainability (tolerance) have been studied at different drain-source and gate-source voltages. A hardware tester circuit was designed and developed to test the devices under such extreme circuit conditions. Then, the gate reliability of SiC MOSFET devices have been compared to that of Si power devices of similar ratings. The results reveal a higher reduction in the instantaneous gate-source voltage of SiC MOSFETs compared to that of Si devices under the same operating conditions. The gate-voltage reduction phenomenon results from the higher leakage currents through the gate. Furthermore, it was found that the gate-source voltage reduction during the test depends on the gate structures. The gate voltage reduction of SiC MOSFETs with planar gate is higher than that of MOSFETs with shield planar gate. As the pulse duration increases in short-circuit tests, the leakage current in the gate-source of SiC devices increases. The results show that even though the SiC MOSFETs are very capable of processing long pulses and high power in the drain-source, the gate-source side is highly degraded by these pulses in the test. Moreover, whenever a small number of the short-circuit tests are applied, the gate structure of SiC MOSFETs becomes broken while the drain-source is still able to block the dc-link voltage. The paper concludes that the short-circuit reliability of the gate was found to be worse compared with commercial Si devices with similar rating.
233 citations
TL;DR: In this paper, the nonlinear characteristics of drain-source capacitance in SiC MOSFETs are studied in detail, and the simplified modeling methods for engineering applications are presented.
Abstract: The nonlinear junction capacitances of power devices are critical for the switching transient, which should be fully considered in the modeling and transient analysis, especially for high-frequency applications. The silicon carbide (SiC) MOSFET combined with SiC Schottky Barrier Diode (SBD) is recognized as the proposed choice for high-power and high-frequency converters. However, in the existing SiC MOSFET models only the nonlinearity of gate-drain capacitance is considered meticulously, but the drain–source capacitance, which affects the switching commutation process significantly, is generally regarded as constant. In addition, the nonlinearity of diode junction capacitance is neglected in some simplified analysis. Experiments show that without full consideration of nonlinear junction capacitances, some significant deviations between simulated and measured results will emerge in the switching waveforms. In this paper, the nonlinear characteristics of drain–source capacitance in SiC MOSFET are studied in detail, and the simplified modeling methods for engineering applications are presented. On this basis, the SiC MOSFET model is improved and the simulation results with improved model correspond with the measured results much better than before, which verify the analysis and modeling.
157 citations
16 Jun 2015
TL;DR: In this paper, the authors propose a 3D VLSI with a CoolCube integration to vertically stack several layers of devices with a unique connecting via density above a million/mm2.
Abstract: 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.
151 citations
TL;DR: In this paper, the authors evaluate the ability of gallium nitride transistors to improve efficiency and output power density in high frequency resonant and soft-switching applications, and experimentally verify the benefits of replacing Si MOSFETs with enhancement mode GaN transistors (eGaNFETs).
Abstract: The emergence of gallium nitride (GaN)-based power devices offers the potential to achieve higher efficiencies and higher switching frequencies than possible with mature silicon (Si) power MOSFETs. In this paper, we will evaluate the ability of gallium nitride transistors to improve efficiency and output power density in high frequency resonant and soft-switching applications. To experimentally verify the benefits of replacing Si MOSFETs with enhancement mode GaN transistors (eGaNFETs) in a high frequency resonant converter, 48–12 V unregulated isolated bus converter prototypes operating at a switching frequency of 1.2 MHz and an output power of up to 400 W are compared using Si and GaN power devices.
147 citations
15 Mar 2015
TL;DR: In this paper, the authors presented the latest 1.2kV and 2.7kV SiC MOSFETs designed to maximize SiC device benefits for high-power, medium voltage power conversion applications.
Abstract: This paper presents the latest 1.2kV–2.2kV SiC MOSFETs designed to maximize SiC device benefits for high-power, medium voltage power conversion applications. 1.2kV, 1.7kV and 2.2kV devices with die size of 4.5mm × 4.5mm were fabricated, exhibiting room temperature on-resistances of 34mOhm, 39mOhm and 41mOhm, respectively. The ability to safely withstand single-pulse avalanche energies of over 17J/cm2 is demonstrated. Next, the 1.7kV SiC MOSFETs were used to fabricate half-bridge power modules. The module typical onresistance was 7mOhm at Tj=25°C and 11mOhm at 150°C. The module exhibits 9mJ turn-on and 14mJ turn-off losses at Vds=900V, Id=400A. Validation of GE's SiC MOSFET performance advantages was done through continuous buck-boost operation with three 1.7kV modules per phase leg exhibiting 99.4% efficiency. Device ruggedness and tolerance to terrestrial cosmic radiation was evaluated. Experimental results show that higher voltage devices (2.2kV and 3.3kV) are more susceptible to cosmic radiation, requiring up to 45% derating in order to achieve module failure rate of 100 FIT, while 1.2kV MOSFETs require only 25% derating to deliver similar FIT rate. Finally, the feasibility of medium voltage power conversion based on series connected 1.2kV SiC MOSFETs with body diode is demonstrated.
124 citations
TL;DR: In this paper, the basic characteristics of a 600 V cascode GaN switch, such as voltage distribution during the turn-on and turn-off transition, were analyzed in detail, including the impact of the package parasitic inductance in both hard and soft switching modes.
Abstract: Gallium nitride (GaN) devices are gathering momentum, with a number of recent market introductions for a wide range of applications such as point-of-load converters, OFF-line switching power supplies, battery chargers, and motor drives. This paper studies the basic characteristics of a 600 V cascode GaN switch, such as voltage distribution during the turn-ON and turn-OFF transition. The switching loss mechanism of the cascode GaN switch is analyzed in detail, including the impact of the package parasitic inductance in both hard- and soft-switching modes. A soft-switching 5 MHz boost converter is developed and shows the advantages and the potential of the cascode GaN.
119 citations
TL;DR: In this article, a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application is presented, where a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated.
Abstract: This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.
104 citations
TL;DR: In this article, the tradeoff between the switching energy and electrothermal robustness is explored for 1.2kV SiC MOSFET, silicon power MOS-FET and 900-V CoolMOS body diodes at different temperatures.
Abstract: The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.
102 citations
TL;DR: In this article, a parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated, which aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties.
Abstract: A parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated. The concept referred to as the cross-switch (XS) hybrid aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties due to the combination of both the bipolar Si IGBT and unipolar SiC MOSFET characteristics. For the purpose of demonstrating the XS hybrid, the parallel configuration is implemented experimentally in a single package for devices rated at 1200 V. Test results are obtained to validate this approach with respect to the static and dynamic performance when compared to a full Si IGBT and a full SiC MOSFET reference devices having the same power ratings as for the XS hybrid samples.
99 citations
TL;DR: In this article, an analytical model for junctionless MOSFET based biosensor for label free electrical detection of biomolecules like enzyme, cell, DNA etc. using the Dielectric Modulation (DM) technique has been developed.
TL;DR: In this paper, a reoxidation process was used to improve the ON-resistance of SiC-MOSFETs with a threshold voltage of 2.9 m at 150 °C.
Abstract: SiC-MOSFETs provide superior performance for next generation power electronics systems. High threshold voltage 600 V SiC-MOSFETs were realized utilizing a reoxidation process, which drastically improves a tradeoff between an ON-resistance and a threshold voltage. Low-loss SiC-MOSFETs with a 1200 V/100-A rating have been developed. Using the developed SiC-MOSFETs, 1200 V/800-A high-power full SiC module with an ON-resistance as low as 2.9 m $\Omega $ at 150 °C was successfully fabricated. The high-power module markedly reduces power loss especially at high carrier frequency. Large-area 3300 V SiC-MOSFETs with an ON-resistance of 52 m $\Omega $ at 175 °C exhibit an adequate reverse bias safe operating area and 3300 V SiC-MOSFETs screened by applying a body diode current stress show stable characteristics under a continuous current through their body diode for 1000 h.
TL;DR: In this article, a p-type, single crystalline, few layer MoS2 field effect transistor (FET) using Niobium (Nb) as the dopant was demonstrated and the doping concentration was determined to be ∼3'×'1019' cm3.
Abstract: We report on the demonstration of a p-type, single crystalline, few layer MoS2 field effect transistor (FET) using Niobium (Nb) as the dopant. The doping concentration was extracted and determined to be ∼3 × 1019/cm3. We also report on bilayer Nb-doped MoS2 FETs with ambipolar conduction. We found that the current ON-OFF ratio of the Nb-doped MoS2 FETs changes significantly as a function of the flake thickness. We attribute this experimental observation to bulk-type electrostatic effect in ultra-thin MoS2 crystals. We provide detailed analytical modeling in support of our claims. Finally, we show that in the presence of heavy doping, even ultra-thin 2D-semiconductors cannot be fully depleted and may behave as a 3D material when used in transistor geometry. Our findings provide important insights into the doping constraints of 2D materials, in general.
TL;DR: In this paper, the GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed to date for ultra-low power analog applications, which can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs.
Abstract: Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the $g_{m}/I_{d}$ integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.
TL;DR: In this paper, the authors show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.
Abstract: We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.
1 Nov 2015
TL;DR: In this article, a simple RC snubber method has been used for dynamic voltage sharing to offset the turn-off delays due to mismatch on device's characteristics and/or gate signals.
Abstract: The low voltage SiC (Silicon carbide) MOSFET (1.2 kV to 1.7 kV) increases the switching frequency limits of a power electronic converter several folds compared to low voltage Si IGBTs. Significant increase in efficiency and power density of voltage source converters can be achieved. However, for medium-voltage high-power converter applications Silicon (Si) devices (4.5 kV and 6.5 kV IGBT) are still dominant. To explore the capability of low voltage SiC devices for medium or high voltage applications, series connection of 1.7 kV/300 A SiC MOSFET modules has been investigated in this paper. A simple RC snubber method has been used for dynamic voltage sharing to offset the turn-off delays due to mismatch on device's characteristics and/or gate signals. Experimental switching characterization with different values of RC snubbers have been carried out to find the optimal RC snubber which gives minimum voltage sharing difference, snubber losses and total semiconductor losses. This paper also intends to show an optimization of the RC snubber for series connection of a limited number of 1.7kV SiC MOSFETs for 6 kV dc bus and for a generalized dc bus voltage.
TL;DR: Experimental robustness tests made on Silicon Carbide (SiC) MOSFETs and SiC Bipolar Junction Transistors (BJTs) submitted to short-circuit operations (SC) or current limitation modes are presented and two main failure modes are pointed out.
TL;DR: It is shown experimentally and theoretically that dIDS/dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off and using fundamental device physics equations, this behavior is predictable.
Abstract: Silicon carbide Schottky barrier diodes (SiC-SBDs) are prone to electromagnetic oscillations in the output characteristics The oscillation frequency, peak voltage overshoot, and damping are shown to depend on the ambient temperature and the metal-oxide- semiconductor field-effect transistor (MOSFET) switching rate (dIDS/dt) In this paper, it is shown experimentally and theoretically that dIDS/dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off As a result, the oscillation frequency and peak voltage overshoot of the SiC-SBD increases with temperature during diode turn-off This temperature dependence of the diode ringing reduces at higher dIDS/dt and increases at lower dIDS/dt It is also shown that the rate of change of dIDS/dt with temperature (d2IDS/dtdT) is strongly dependent on RG and using fundamental device physics equations, this behavior is predictable The dependence of the switching energy on dIDS/dt and temperature in 12-kV SiC-SBDs is measured over a wide temperature range (-75 °C to 200 °C) The diode switching energy analysis shows that the losses at low dIDS/dt are dominated by the transient duration and losses at high dIDS/dt are dominated by electromagnetic oscillations The model developed and results obtained are important for predicting electromagnetic interference, reliability, and losses in SiC MOSFET/SBDs
TL;DR: In this article, the effects of doping concentration and temperature upon the transport properties in the channel of lateral n-channel SiC MOSFETs have been studied using current-voltage and Hall-effect measurements.
Abstract: The effects of doping concentration and temperature upon the transport properties in the channel of lateral n-channel SiC MOSFETs have been studied using current–voltage and Hall-effect measurements. To interpret the electrical measurements, numerical TCAD simulations have been performed. A simulation methodology that includes the calculation of the Hall factor in the channel of SiC MOSFETs has been developed and applied. In addition, a new model for the bulk mobility has been suggested to explain the temperature dependence of the MOSFET characteristics with different background doping concentrations. Based on the good agreement between the simulated and the measured results, scattering mechanisms in the channel of SiC MOSFETs have been studied.
29 Oct 2015
TL;DR: In this paper, a simple and accurate analytical loss model for Silicon Carbide (SiC) power devices is proposed, which considers the package and PCB parasitic elements in the circuits, nonlinearity of device junction capacitance and ringing loss.
Abstract: In this paper, a simple and accurate analytical loss model for Silicon Carbide (SiC) power devices is proposed. A novel feature of this loss model is that it considers the package and PCB parasitic elements in the circuits, nonlinearity of device junction capacitance and ringing loss. The proposed model identifies the switching waveform subintervals, and develops the analytical equations in each switching subinterval to calculate the switching loss. Inductive turn-on and turn-off are thoroughly analyzed. A double pulse test-bench is built to characterize inductive switching behavior of the SiC devices. The analytical results are compared with experimental results. The results show that the proposed loss model can predict switching loss more accurately than the conventional loss model.
TL;DR: In this article, simple and accurate circuit simulation models for high-voltage silicon carbide power MOSFETs and Schottky barrier diodes are presented and validated.
Abstract: Simple and accurate circuit simulation models for high-voltage silicon carbide power MOSFETs and Schottky barrier diodes are presented and validated. The models are physics-based and consist of minimal number of model parameters that can be easily extracted from simple static $I$ – $V$ and $C$ – $V$ measurements. The models are used in a buck-boost bidirectional dc-dc converter, with and without an antiparallel Schottky diode. The efficiency of the converter was analyzed for synchronous and nonsynchronous operation of the switches. An optimal selection of the antiparallel Schottky diode is proposed to minimize the cost of the converter without compromising its efficiency.
TL;DR: In this article, a photonic control mechanism is proposed to control the switching dynamics of an optically triggered hybrid device, which comprises a power MOSFET, as the main power semiconductor device (PSD), and a pair of GaAs-based Optically Triggered Power Transistors (OTPTs), serving as the driver for the PSD.
Abstract: To control the switching dynamics of an optically triggered hybrid device, a photonic-control mechanism is outlined. The optically triggered hybrid device comprises a power MOSFET, as the main power semiconductor device (PSD), and a pair of GaAs-based optically triggered power transistors (OTPTs), serving as the driver for the power MOSFET . The switching-transition controller modulates the turn-off transition of the power MOSFET by modulating the optical intensity of the OTPTs. The independent and unified $dv/dt$ and $di/dt$ control of the PSD is achieved using a single control circuit which also predicts the onset of transition between the $di/dt$ and the $dv/dt$ regions of control. Experimental control results validating the OTPT-based dynamical modulation of the turn-off characteristic of the power MOSFET are provided. In this study, the power MOSFET is chosen to be a SiC mosfet . However, the proposed photonic-control mechanism can be extended to Si power MOSFETS as well.
1 Nov 2015
TL;DR: In this paper, an integrated SiC module with 1.2kV MOSFETs bare dies and two high current gate driver chips is integrated in a compact integrated module package to reduce the parasitic inductance.
Abstract: With the commercialization of wide bandgap power devices such as SiC MOSFETs and JBS diodes, power electronics converters used in the harsh environments such as hybrid electric vehicles and aerospace attract more and more attentions. The low loss, high temperature and fast switching capabilities are utilized in the converters to improve the power density and efficiency. However, the EMI problem caused by the fast switching is a major constrain for improving switching frequency. For this reason, an integrated SiC module with 1.2kV MOSFET and ultra-fast gate drive circuits is proposed and developed. Two 1.2kV SiC MOSFETs bare dies and two high current gate driver chips are integrated in a compact integrated module package to reduce the parasitic inductance. 0Ω gate resistor therefore can be used in this module to improve the device at maximum speed. Noise free operation of the tested module is verified even under extremely high dV/dt and dI/dt conditions. The ultra-low turn-off loss of the module is being demonstrated. Finally, the integrated module is demonstrated in two megahertz converters: an 800W 1.5MHz synchronous boost converter and a 3.38MHz half bridge inverter. The era for high voltage-megahertz switching has arrived.
TL;DR: This paper presents the design process of a 312-kVA three-phase silicon carbide inverter using ten parallel-connected metal-oxide-semiconductor field-effect-transistor power modules in each phase leg and results showing proper steady-state operation of the power converter are presented.
Abstract: This paper presents the design process of a 312-kVA three-phase silicon carbide inverter using ten parallel-connected metal–oxide–semiconductor field-effect-transistor power modules in each phase leg. The design processes of the gate-drive circuits with short-circuit protection and power circuit layout are also presented. Measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Moreover, electrical and thermal measurements in order to evaluate the transient performance and steady-state operation of the parallel-connected power modules are shown. Experimental results showing proper steady-state operation of the power converter are also presented. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been measured for the inverter.
TL;DR: In this article, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band of silicon-carbide (SiC) is proposed, which utilizes transient current measurements on 4H-SiC MOS capacitors biased in accumulation.
Abstract: Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method.
3 May 2015
TL;DR: In this paper, the authors provide guidance on how to design gate driver circuits for Silicon Carbide (SiC) MOSFETs, which are much faster and more efficient than their traditional IGBT counterparts.
Abstract: The purpose of this paper is to provide guidance on how to design gate driver circuits for Silicon Carbide (SiC) MOSFETs. There are new commercially available SiC MOSFETs available in discrete and module packages which are much faster and more efficient than their traditional IGBT counterparts. To take full advantage of these benefits we need to understand the requirements for a new breed of gate drivers that are tailored to meet the unique drive and protection characteristics of SiC MOSFETs. Traditional IGBT based fault protection schemes such as desaturation (desat) detection can be implemented with some modifications to protect SiC MOSFETs. However, due to the higher switching speed of the new SiC devices, it is worth another look at all the design and implementation aspects of a good SiC MOSFET gate driver.
10 May 2015
TL;DR: In this paper, a multiple stepped oxide field plate (FP) and super junction (SJ) structure was proposed for lowvoltage power MOSFETs to reduce on-resistance drastically.
Abstract: For low-voltage power MOSFETs technology, Field Plate (FP) and Superjunction (SJ) structures have been applied to reduce on-resistance drastically. As one of the approach for the ultimate structure realization, we propose a multiple stepped oxide FP-MOSFET (MSO-FP-MOSFET) that is extremely close to ideal gradient oxide structure. We have validated an optimum device structure by TCAD simulation and achieved lowest on-resistance of 28.5 mΩmm2 at breakdown voltage of 115.2 V. This performance indicates 25 % improvement compared to conventional devices. Moreover, to demonstrate the MSO-FP-MOSFET characteristics for the first time, we present some measurement data of TEG samples.
TL;DR: In this article, a new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed.
Abstract: A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness.
TL;DR: In this paper, the authors investigated the difference between planar and FinFET devices in terms of soft error rate (SER) and found that the reduction in sensitivity of planar MOSFETs is primarily due to an increase in the threshold LET and a reduction in the sensitive volume due to the shape of the transistor.
Abstract: The assessment of the soft-error rate (SER) of semiconductor devices continues to be important, even with the adoption of FinFET devices which overcome some important limitations of planar MOSFETs. The study in this paper presents both theoretical and experimental results via advanced simulation techniques, to investigate the difference between planar and FinFET devices in terms of SER. Neutron test results from different facilities are presented, and the observed differences in sensitivity are explained through theoretical analysis. In the second half of the paper, the test results are validated through TCAD and TFIT simulations using a calibrated technology response model. The analysis shows that the reduction in sensitivity of FinFET devices is primarily due to an increase in the threshold LET and a reduction in the sensitive volume due the shape of the transistor.
TL;DR: In this article, a new analytical approach is proposed to extract the gate dependent threshold voltage for cylindrical gate tunnel FETs (CG-TFETs) by using peak transconductance change method based on the saturation of tunneling barrier width.