Abstract: This paper presents an accurate analytical model to calculate the power loss of a high voltage Gallium Nitride high electron mobility transistor (GaN HEMT) in cascode configuration. The proposed model considers the package and PCB parasitic inductances, the nonlinearity of the junction capacitors, and the transconductance of the cascode GaN transistor. The switching process is illustrated in detail, including the interaction of the low voltage Si MOSFET and the high voltage GaN HEMT in cascode configuration. The switching loss is obtained by solving the equivalent circuits during the switching transition. The analytical results show that the turn-on loss dominates in hard-switching conditions while the turn-off loss is negligible, due to the intrinsic current source driving mechanism. The accuracy of the proposed model is validated by numerous experimental results. The results of both the analytical model and experiments suggest that soft-switching is critical for high voltage GaN in high-frequency high-efficiency applications.

Abstract: In this paper, a high-temperature, high-frequency, wire-bond-based multichip phase-leg module was designed, fabricated, and fully tested. Using paralleled Silicon Carbide (SiC) MOSFETs, the module was rated at 1200 V and 60 A, and was designed for a 25-kW three-phase inverter operating at a switching frequency of 70 kHz, and in a harsh environment up to 200 °C, for aircraft applications. To this end, the temperature-dependent characteristics of the SiC MOSFET were first evaluated. The results demonstrated the superiority of the SiC MOSFET in both static and switching performances compared to Si devices, but meanwhile did reveal the design tradeoff in terms of the device's gate oxide stability. Various high-temperature packaging materials were then extensively surveyed and carefully selected for the module to sustain the harsh environment. The electrical layout of the module was also optimized using a modeling and simulation approach, in order to minimize the device parasitic ringing during high-speed switching. Finally, the static and switching performances of the fabricated module were tested, and the 200 °C continuous operation of the SiC MOSFETs was verified.

Abstract: Power switching devices based on wide bandgap semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN) offer superior performance such as low switching and conduction losses, high voltage, high frequency, and high temperature operation. In this paper, a 600-V GaN switch and a 600-V GaN diode were tested in detail to understand the GaN device capabilities with respect to equivalent silicon-based devices such as IGBT and MOSFET. Detailed experimental loss models are developed and compared with datasheet models. Experimental setup of different power converters such as boost, buck-boost, and half-bridge inverter and associated comparative experimental results are presented. This paper also presents the investigations into the effectiveness of using GaN devices and higher switching frequencies in reducing the total size and cost of power conversion equipment such as an online UPS system.

Abstract: Contact resistance (Rc) can substantially obscure the extracted mobility based on standard transconductance or two-point conductance measurements of field-effect devices especially for low density of states materials such as MoS2 or similar atomic crystals. Currently, there exists a pressing need for a routine technique that can decouple mobility extraction from Rc. By combining experiments and analysis, we show that the Y-function method offers a robust route for evaluating the low-field mobility, threshold voltage and Rc even when the contact is a Schottky-barrier as is common in two-dimensional transistors. In addition, an independent modified transfer length method evaluation corroborates the Y-function analysis.

Abstract: By forming a highly stable Al2O3 gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (VB) of the MOSFET without a field plate is 600 V at a gate-drain distance (LGD) of 7 μm. We fabricated some MOSFETs for which VB/LGD > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al2O3 was deposited on the C-H surface by atomic layer deposition (ALD) at 450 °C using H2O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

Abstract: Wide band-gap (WBG) field-effect devices are known to provide a system-level performance benefit compared to silicon devices when integrated into power electronics applications. However, the near-ideal features of these switching devices can also introduce unexpected behavior in practical systems due to the presence of parasitic elements. The occurrence of self-sustained oscillation is one such behavior that has not received adequate study in the literature. This paper provides an analytical treatment of this phenomenon by casting the switching circuit as an unintentional negative resistance oscillator. This treatment utilizes an established procedure from the oscillator design literature and applies it to the problem of power circuit oscillation. A simulation study is provided to identify the sensitivity of the model to various parameters, and the predictive value of the model is confirmed by experiment involving two exemplary WBG devices: a SiC vertical-channel JFET and a SiC lateral-channel MOSFET. The results of this study suggest that susceptibility to self-sustained oscillation is correlated to the available power density of the device relative to the parasitic elements in the circuit, for which wide band-gap devices, to include SiC and GaN transistors, are in a class approaching that of the radio frequency domain.

Abstract: There is little work done to study the nuances related to paralleling the higher speed SiC Mosfet devices when compared to Si devices. This paper deals with the parallel operation of packaged silicon carbide (SiC) MOSFETs. The parameters that affect the static and dynamic current sharing behavior of the devices have been studied. We also investigate the sensitivity of those parameters to the junction temperature of the devices. The case temperature difference for paralleled MOSFETs has been experimentally measured on a SEPIC converter for different gate driver resistance and different switching frequency, the results show the current and temperature can be well balanced for the latest generation of SiC MOSFETs with low gate driver resistance.

Abstract: SiC MOSFET devices have great potentials in future high temperature power electronics applications due to their possible higher thermal runaway temperature compared with other SiC power semiconductor devices. In this paper, the high temperature stability of SiC MOSFETs is investigated by experiments and Saber simulations. The maximum steady-state junction temperature of the SiC MOSFET is measured to exceed 250 °C and saber simulations based on experimental model estimate that the thermal runaway temperatures are close to 300 °C. In addition, performance degradation of SiC MOSFETs during high-temperature operation is observed and discussed. Experimental results show that the degradation happens during both the high temperature storage (maximum 5% RON increment) and high temperature operation process (maximum 15% RON increment). The degradations are found to recover to a close-to-initial level after 1 h recovery time at the room temperature.

Abstract: Wide band gap semiconductors, and in particular silicon carbide (4H-SiC) and gallium nitride (GaN), are very promising materials for the next generation of power electronics, to guarantee an improved energy efficiency of devices and modules. As a matter of fact, in the last decade intensive academic and industrial research efforts have resulted in the demonstration of both 4H-SiC MOSFETs and GaN HEMTs exhibiting VB2/Ron performances well beyond the silicon limits. In this paper, some of the present scientific challenges for SiC and GaN power devices technology are reviewed. In particular, the topics selected in this work will be the SiO2/SiC interface passivation processes to improve the channel mobility in 4H-SiC MOSFETs, the current trends for gate dielectrics in GaN technology and the viable routes to obtain normally-off HEMTs.

Abstract: Under realistic switching conditions, SiC MOSFETs reliability issues remain as a challenge that requires further investigation. In this letter, a specific aging test has been developed to monitor and characterize the electrical parameters of the SiC MOSFET. This allows estimations of the health state and predictions of the remaining lifetime prior to its failure. The gate leakage current seems to be a relevant runaway parameter just before failure. This leakage indicates deterioration of the gate structure. This hypothesis has been validated through analysis of scanning electron microscopy pictures, with a focused ion beam cut showing cracks within the polysilicon.

Abstract: The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 1012 on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 °C. A simple 1T process and a considerably low OFF-state leakage of 3×10-12 A/μm were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-κ CMOS processing.

Abstract: With the commercial availability of SiC power devices, their acceptance is expected to grow in consideration of the excellent low switching loss, high-temperature operation, and high-voltage rating capabilities of these devices. This paper presents the comparative performance evaluation of different SiC power devices in the matrix converter at various temperatures and switching frequencies. To this end, first, gate or base drive circuits for normally-off SiC JFET, SiC MOSFET, and SiC BJT by taking into account the special demands for these devices are presented. Then, four two-phase to one-phase matrix converters are built with different Si and SiC power devices to measure the switching waveforms and power losses for them at different temperatures and switching frequencies. Based on the measured data, four different SiC and Si power devices are compared in terms of switching times, conduction and switching losses, and efficiency at different temperatures and switching frequencies. Furthermore, a theoretical investigation of the power losses of the three-phase matrix converter with normally-off SiC JFET, SiC MOSFET, SiC BJT, and Si IGBT is described. The power losses estimation indicates that a 7-kW matrix converter would potentially have an efficiency of approximately 94% in high switching frequency if equipped with SiC devices.

Abstract: An improved model of medium voltage (1200 V) silicon carbide (SiC) MOSFET based on PSpice is proposed in this paper, which is suitable for wide temperature range applications especially at low temperature. The static characteristics of SiC MOSFET are described by introducing temperature-dependent voltage source and current source. The effect of negative turn-off gate drive voltage is also taken into account in the modeling. In order to reflect the low-temperature characteristics of SiC MOSFET accurately, low temperature (-25 °C) measurements are carried out, which provide the modeling basis. The determinations of key parameters in the model are analyzed in detail, including the on-state resistor, internal gate resistor, temperature dependent sources, and some capacitors. The proposed model is verified by the experimental tests on a buck converter prototype at different input voltages, input currents, and temperatures. Simulation results on the proposed model coincide well with the experimental test results, in terms of switching waveforms and power losses even at low temperature (-25 °C). These results demonstrate that the proposed model exhibits high accuracy within wide temperature range.

Abstract: With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

Abstract: In this paper, a new series connection topology is introduced for silicon carbide (SiC) MOSFETs. In the topology, with a single external gate drive, three series-connected SiC MOSFETs are synchronously driven. The operating principle of the proposed topology is analyzed and presented. In order to improve the current capability of the module, parallel connection of two SiC devices are also demonstrated. A 3600 V/80 A series-parallel-connected configuration with three rows in a series and two branches in parallel is constructed with six 1200 V/40 A discrete SiC MOSFETs. Switching behavior of the configuration is completed at 2300 V/78 A. Experimental results verify the validity and feasibility of the proposed topology. Analysis based on experimental results for the circuit switching speed and switching losses is given. Finally, such a series-parallel-connected circuit is integrated in a SiC MOSFETs module, capable of 3600 V/80 A. The switching characteristics of the module are compared to the discrete configuration.

Abstract: Although the traditional metal-on-semiconductor field-effect transistor (MOSFET) has been a workhorse in information processing for decades, we must now consider its successor. To make spintronics a reality, by analogy we need a ``spin MOSFET''. The authors demonstrate room-temperature operation of just such a device, in which a flow of spin angular momentum in nondegenerate silicon is controlled by an external gate voltage.

Abstract: Co-fabrication of a nanoscale vacuum field emission transistor (VFET) and a metal-oxide-semiconductor field effect transistor (MOSFET) is demonstrated on a silicon-on-insulator wafer. The insulated-gate VFET with a gap distance of 100 nm is achieved by using a conventional 0.18-μm process technology and subsequent photoresist ashing process. The VFET shows a turn-on voltage of 2 V at a cell current of 2 nA and a cell current of 3 μA at the operation voltage of 10 V with an ON/OFF current ratio of 10 $^{4}$ . The gap distance between the cathode and anode in the VFET is defined to be less than the mean free path of electrons in air, and consequently, the operation voltage is reduced to be less than the ionization potential of air molecules. This allows the relaxation of the vacuum requirement. The present integration scheme can be useful as it combines the advantages of both structures on the same chip.

Abstract: We study the transport properties of monolayer MX2 (M = Mo, W; X = S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX2 MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX2 MOSFETs.

Abstract: This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.

Abstract: This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

Abstract: We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Abstract: Voltage sourced converters (VSCs) in electric vehicle (EV) drive-trains are conventionally implemented by silicon Insulated Gate Bipolar Transistors (IGBTs) and p-i-n diodes. The emergence of SiC unipolar technologies opens up new avenues for power integration and energy conversion efficiency. This paper presents a comparative analysis between 1.2-kV SiC MOSFET/Schottky diodes and silicon IGBT/p-i-n diode technologies for EV drive-train performance. The switching performances of devices have been tested between -75 °C and 175 °C at different switching speeds modulated by a range of gate resistances. The temperature impact on the electromagnetic oscillations in SiC technologies and reverse recovery in silicon bipolar technologies is analyzed, showing improvements with increasing temperature in SiC unipolar devices whereas those of the silicon-bipolar technologies deteriorate. The measurements are used in an EV drive-train model as a three-level neutral point clamped VSC connected to an electric machine where the temperature performance, conversion efficiency and the total harmonic distortion is studied. At a given switching frequency, the SiC unipolar technologies outperform silicon bipolar technologies showing an average of 80% reduction in switching losses, 70% reduction in operating temperature and enhanced conversion efficiency. These performance enhancements can enable lighter cooling and more compact vehicle systems.

Abstract: This paper presents a comparison of the behavior of the intrinsic diode of silicon (Si) and silicon carbide (SiC) MOSFETs. The study was done for 1200 V Si and SiC MOSFETs. The data sheet from manufacturers shows the characteristics of MOSFET' intrinsic diode when gate source voltage (VGS) is 0 V. There are applications where the MOSFET' intrinsic diode is used while VGS is different than 0 V. One of these applications is induction heating, where depending on the load and the regulation system, the diode can conduct a significant part of the inverter current. In most applications which use the MOSFET' intrinsic diode, the turn ON of the intrinsic diode happens at VGS = 0 V. After a blanking time, the MOSFET' gate is activated waiting for the direction change of current in the circuit. Therefore, most of the current through the MOSFET' intrinsic diode occurs with a VGS different of 0 V. This paper shows the direct output characterization of Si and SiC MOSFET' intrinsic diode under different gate voltages. The gate resistor (RG) is an important parameter of the characterization. Depending on the input capacitance of the Si or SiC MOSFET, different RG are needed. The turn-on and turn-off behaviors are obtained when RG is optimized for each Si and SiC MOSFET. This has result in the turn-off robustness of intrinsic diode with optimum RG. This paper presents a surprising result for the reverse characteristic of Si and SiC MOSFETs for the same current at different VGS. The technology of Si MOSFET has different behavior depending on the manufacturer. The technology of SiC MOSFET presents a very similar behavior to low-voltage Si MOSFETs.

Abstract: Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (- and -), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Abstract: This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl3/SiCl4/Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10). To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O2 plasma oxidation and diluted H2SO4 rinse. Using these technologies, we demonstrate vertical InGaAs gateall-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs.

Abstract: An experimental and simulation study of short- channel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling. Index Terms— Low-power (LP) logic circuits, mobility enhancement, oxygen insertion (OI), super-steep retrograde well (SSRW), variability.

Abstract: A novel structure of tunnel field-effect transistor (FET) is introduced with the gate composed of three segments of different work functions. The tunnel current is controlled by an in channel potential barrier as well as the source-channel tunnel junction bandgap, which combines the merits of both bandgap-controlled tunnel FET and barrier-controlled traditional MOSFET. Intuitive explanation is provided for this novel device structure. The performance enhancement is confirmed by numerical simulation with carbon nanotube as the channel material. This structure is especially suitable for bandgap tunable ballistic transport materials (e.g., carbon nanotube and graphene nanoribbon).

Abstract: In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.