Abstract: In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.

Abstract: A gate-insulated vacuum channel transistor was fabricated using standard silicon semiconductor processing. Advantages of the vacuum tube and transistor are combined here by nanofabrication. A photoresist ashing technique enabled the nanogap separation of the emitter and the collector, thus allowing operation at less than 10 V. A cut-off frequency fT of 0.46 THz has been obtained. The nanoscale vacuum tubes can provide high frequency/power output while satisfying the metrics of lightness, cost, lifetime, and stability at harsh conditions, and the operation voltage can be decreased comparable to the modern semiconductor devices.

Abstract: To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.

Abstract: In 2011, after many years of research and development SiC power MOSFETs became available in the commercial marketplace. This paper presents the results of Co60 total ionizing dose (TID) effects for the new high power-high current 24 A SiC devices irradiated at room temperature and 125°C. These commercially available components remained operational after a radiation dose of more than 100 krad. However, gamma ray irradiation gave rise to changes in current-voltage and capacitance-voltage characteristics. Specifically, threshold voltage decreased, resulting in increased current drive. We also observed rises in interface state densities, as well as input, output and reverse transfer capacitances with increasing accumulated doses.

Abstract: In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current.

Abstract: The introduction of Gallium Nitride (GaN) based power devices offers the potential to achieve higher efficiency and higher switching frequencies than possible with Silicon MOSFET's. This paper will discuss the GaN device characteristics, packaging impact on performance, gate driving methods, and the integration possibilities using GaN technology. The final demonstration being an integrated 3D point of load (POL) converter operating at a switching frequency of 2MHz for a 12V to 1.2V buck converter with a full load current of 20A. This 3D converter employs a low profile low temperature co-fired ceramic (LTCC) inductor and can achieve a full load efficiency of 83% and a power density of 750W/in3 which doubles the power density of current integrated POL converters on the market today.

Abstract: In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

Abstract: In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current (Ids) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency (fT) and maximum oscillation frequency (fMAX) along with 65% improvement in voltage gain (AVO) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors.

Abstract: We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

Abstract: A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao-Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET.

Abstract: A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Abstract: Emerging nonvolatile memory with an oxide-semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The memory is called nonvolatile oxide-semiconductor random access memory (NOSRAM). The memory cell of the NOSRAM (NOSRAM cell) consists of an IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) for data reading, and a cell capacitor for storing charge and controlling the PMOS gate voltage. The IGZO TFT and the cell capacitor are formed over the PMOS. Owing to extremely low-leakage-current characteristics of the IGZO TFT, the charge stored in the 2-fF cell capacitor is maintained for a long time. This long data retention realized innovative nonvolatile memory. The NOSRAM cell fabricated with the 0.8-μ m process technology demonstrated an on/off ratio of 107 and an endurance over 1012 write cycles. In addition, NOSRAM with a memory capacity of 1 Mb was fabricated; the cell size was 12.32 μm2 and the cell array size was 13.5 mm2. The 1-Mb NOSRAM achieved basic operation at 4.5 V or less, write operation at 150 ns/page, read distribution of data “1” with 3σ = 0.10 V, and a data retention over 60 days at 85°C.

Abstract: We present tunneling field-effect transistors fabricated from InP-GaAs heterostructure nanowires with an n-i-p doping profile, where the intrinsic InP region is modulated by a top gate. The devices show an inverse subthreshold slope down to 50 mV/dec averaged over two decades with an on/off current ratio of approximately 10(7) for a gate voltage swing (V(GS)) of 1 V and an on-current of 2.2 μA/μm. Low-temperature measurements suggest a mechanism of trap-assisted tunneling, possibly explained by a narrow band gap segment of InGaAsP.

Abstract: Silicon Carbide (SiC) devices and modules have been developed with high blocking voltages for Medium Voltage power electronics applications. Silicon devices do not exhibit higher blocking voltage capability due to its relatively low band gap energy compared to SiC counterparts. For the first time, 12kV SiC IGBTs have been fabricated. These devices exhibit excellent switching and static characteristics. A Three-level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) has been simulated with newly developed SiC IGBTs. This 3L-NPC Converter is used as a 7.2kV grid interface for the solid state transformer and STATCOM operation. Also a comparative study is carried out with 3L-NPC VSC simulated with 10kV SiC MOSFET and 6.5kV Silicon IGBT device data.

Abstract: Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

Abstract: In many pulsed-power applications, there is a trend to modulators based on semiconductor technology For these modulators, high-voltage and high-current semiconductor switches are required in order to achieve a high pulsed power Therefore, often, high-power IGBT modules or IGCT devices are used Since these devices are based on bipolar technology, the switching speed is limited, and the switching losses are higher In contrast to bipolar devices, unipolar ones (eg, SiC JFETs) basically offer a better switching performance Moreover, these devices enable high blocking voltages in the case where wide-band-gap materials, for example, SiC, are used At the moment, SiC JFET devices with a blocking voltage of 12 kV per JFET are available Alternatively, the operating voltage could be increased by connecting N JFETs and a low-voltage MOSFET in series, resulting in a super cascode switch with a blocking voltage N times higher than the blocking voltage of a single JFET For the super cascode, auxiliary elements are required for achieving a statically and dynamically balanced voltage distribution in the cascode In this paper, a new balancing circuit, which results in faster switching transients and higher possible operating pulse currents, is presented and validated by measurement results

Abstract: The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12-nm technology node, this paper assesses the performance of the In0.75Ga0.25As of III-V semiconductor compounds and strained-Si channel nanoscale transistors with identical dimensions. The impact of the channel material property and the device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. Two-dimensional and three-dimensional real-space ballistic quantum transport models are employed with band structure nonparabolicity. The simulation results indicate three conclusions: 1) the In0.75Ga0.25As FETs do not outperform strained-Si FETs; 2) triple-gate Fin-shaped Field Effect Transistor (FinFET) surely represent the best architecture for sub-15-nm gate contacts, independently from the material choice; and 3) the simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.

Abstract: Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO2/Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO2/Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO2-based RRAM is a prospective alternative for nonvolatile multilevel memory device applications.

Abstract: A detailed simulation and experimental study of MOSFET mobility enhancement and electrostatic integrity improvement achieved by the insertion of oxygen layers within the Si channel region is presented. The applicability of this technology to thin-body MOSFET structures is discussed. Projections indicate that it will be more effective than strain for boosting performance at the 14 nm node.

Abstract: Gallium Nitride HFET (Hetero-junction Field Effect Transistors) power switches are poised to replace silicon MOSFETs and IGBTs in many high-performance power switching applications. To realize the benefits of these fast-switching GaN devices, special circuit and packaging techniques are necessary. Drive circuits are significantly improved compared to conventional silicon MOSFET drivers. SMD packaging techniques are employed to minimize source inductance. The gate drive provides rise time of a few ns, and drain voltage slew rates of more than 80 V/ns are observed. These circuits are used for double-pulse switching performance characterization and in a synchronous boost converter operating under the same switching conditions. The GaN HFETs switch 350V and 20A in 15 ns with switching energy of 68 μJ. The 1MHz 300V synchronous switching boost converter is 94% efficient, with an output power of 1.2KW.

Abstract: A spin dependent recombination (SDR) spectrum observed in a wide range of SiC metal oxide semiconducting field effect transistors (MOSFETs) has previously been only tentatively linked to a silicon vacancy or vacancy related defect. By resolving hyperfine interactions in SDR detected spectra with 13C nuclei, we provide an extremely strong argument identifying the SDR spectrum with a silicon vacancy. Since the silicon vacancy spectrum dominates the SDR response in a wide variety of SiC MOSFETs, silicon vacancies are quite important traps in this technology.

Abstract: The main goal of this paper is development of a new circuit-based silicon carbide (SiC) DMOSFET model which physically represents the mechanism of current saturation in power SiC DMOSFET. Finite-element simulations show that current saturation for a typical device geometry is due to 2-D carrier distribution effects in the JFET region caused by current spreading from the channel to the JFET region. For high drain-source voltages, most of the voltage drop occurs in the current spreading region located in the JFET region close to the channel. A new model is proposed that represents the nonuniform current distribution in the JFET region using a nonlinear voltage source and a resistance network. Advantages of the proposed model are that a single set of equations describes operation in both the linear and saturation regions, and that it provides a more physical description of MOSFET operation.

Abstract: We have developed a self-aligned Lg = 55 nm In0.53Ga0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n++ In0.53Ga0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n++ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing fmax of 292 GHz and ft of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

Abstract: The Gallium Nitride (GaN) transistors offer the capability of high efficiency at high operation frequency. This paper will discuss the characteristics of enhancement mode and depletion mode GaN transistors; the high frequency GaN converter design considerations include gate driving, reducing dead-time loss, minimizing parasitics inductance, and the three dimension (3D) technology to integrate the active layer with low profile low temperature co-fired ceramic (LTCC) magnetic substrate to achieve high power density. The final demonstrations are two 12 V to 1.2 V conversion integrated point of load (POL) modules: a single-phase10A 800W/in3 5MHz converter, a two-phase 20 A 1000 W/in3 5 MHz converter using the depletion mode GaN transistors. These converters offer unmatched power density compared to state-of-the-art industry products and research.

Abstract: We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.

Abstract: This letter demonstrates a new technology for the heterogeneous integration of GaN and Si devices, which is scalable at least up to 4-in wafers and compatible with conventional Si fabrication. The key step in the proposed technology is the fabrication of a Si (100)-GaN-Si hybrid wafer by bonding a silicon (100) on insulator (SOI) wafer to the nitride surface of an AlGaN/GaN on Si (111) wafer. A thin layer of silicon oxide is used to enhance the bonding between the SOI and the AlGaN/GaN wafers. Using this technology, Si pMOSFETs and GaN high-electron-mobility transistors have been fabricated on a 4-in hybrid wafer. Due to the high-temperature stability of GaN as well as the high-quality semiconductor material resulting from the transfer method, these devices exhibit excellent performance. A hybrid power amplifier has been fabricated as a circuit demonstrator, which shows the potential to integrate GaN and Si devices on the same chip to enable new performance in high-efficiency power amplifiers, mixed signal circuits, and digital electronics.