Abstract: We have fabricated single-wall carbon nanotube field-effect transistors (CNFETs) in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric These top gate devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V—a significant improvement relative to previously reported CNFETs which used the substrate as a gate and a thicker gate dielectric Our measured device performance also compares very well to state-of-the-art silicon devices These results are observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si MOSFETs for future nanoelectronic applications

Abstract: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

Abstract: The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.

Abstract: Silicon offers multiple advantages to power circuit designers, but at the same time suffers from limitations that are inherent to silicon material properties, such as low bandgap energy, low thermal conductivity, and switching frequency limitations. Wide bandgap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), provide larger bandgaps, higher breakdown electric field, and higher thermal conductivity. Power semiconductor devices made with SiC and GaN are capable of higher blocking voltages, higher switching frequencies, and higher junction temperatures than silicon devices. SiC is by far the most advanced material and, hence, is the subject of attention from power electronics and systems designers. This paper looks at the benefits of using SiC in power electronics applications, reviews the current state of the art, and shows how SiC can be a strong and viable candidate for future power electronics and systems applications.

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

Abstract: One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

Abstract: Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).

Abstract: The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

Abstract: Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.

Abstract: A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.

Abstract: Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.

Abstract: A novel local strained channel (LSC) MOSFET has been fabricated by a stress control technique utilizing a strained poly silicon gate electrode The residual compressive stress in arsenic (As) implanted polysilicon is induced by high temperature annealing of CVD SiO/sub 2/ cap with high tensile stress On the other hand, boron (B) implanted poly silicon is free from stress As a result, the only n-channel region is locally strained by the strained polysilicon electrode The drain current of LSC nFETs is improved 15% compared to that of the conventional nFET without the degradation of pFET drain current High performance 55nm CMOSFET is realized by simple process for LSC-structure

Abstract: Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-/spl mu/m generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.

Abstract: We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Abstract: We explore the scaling limits of alternative gate dielectrics based on their direct tunneling characteristics and gate leakage requirements for future complementary metal–oxide–semiconductor technology generations. Important material parameters such as the tunneling effective mass are extracted for several promising high-κ gate dielectrics. We also introduce a figure of merit for comparing the relative advantages of gate dielectric candidates. Using an accurate direct tunneling gate current model and specifications from the International Technology Roadmap for Semiconductors, we provide guidelines for the selection of gate dielectrics to satisfy the off-state leakage current requirements of future high-performance and low power technologies.

Abstract: This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

Abstract: An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors.

Abstract: We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Abstract: A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: By using the non-equilibrium Green's function approach, we report a comprehensive and rigorous study of source-to-drain tunneling in MOSFETs at the scaling limit. The dependence of source-to-drain tunneling on channel length, electrostatics, ambient temperature and scattering is examined, and the effects of source-to-drain tunneling on device characteristics and design issues are explored as well. The results show that source-to-drain tunneling does set an ultimate scaling limit but that this limit is well below 10 nm.

Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.

Abstract: A disk drive is disclosed comprising a disk and a head actuated over the disk. The head comprising a first head terminal and a second head terminal. The disk drive further comprises an electrostatic discharge (ESD) protection circuit comprising a first depletion mode metal oxide semiconductor field effect transistor (MOSFET) and a second depletion mode MOSFET. A first transistor terminal of the depletion mode MOSFETs are coupled to respective head terminals, and a second transistor terminal of the depletion mode MOSFETs are coupled to ground. The gate terminals of the first and second depletion mode MOSFETs are biased to turn on the depletion mode MOSFETs while the disk drive is powered down, thereby grounding the first and second head terminals to protect the head from ESD.

Abstract: A simple model for ballistic nanotransistors, which extends previous work by treating both the charge control and the quantum capacitance limits of MOSFET-like transistors, is presented. We apply this new model to MOSFET-like carbon nanotube FETs (CNTFETs) and to MOSFETs at the scaling limit. The device physics for operation at ballistic and quantum capacitance limits are explored. Based on the analysis of recently reported CNTFETs, we compare CNTFETs to MOSFETs. The potential performance advantages over Si that might be achieved at the scaling limit are established by using the new model.

Abstract: We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.

Abstract: We describe the fabrication of single-wall carbon nanotube field-effect transistors in a conventional metal–oxide–semiconductor field-effect transistor structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric. We use these devices to study the performance improvements achieved by reducing the gate-to-channel separation. The top gate structure offers certain structural advantages over earlier, back gated carbon nanotube devices. In addition, these devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V. The measured device characteristics are significantly better than previously reported carbon nanotube devices, providing further motivation to explore the use of carbon nanotubes for future nanoelectronic applications.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a high speed field effect transistor with low power consumption by using the combination of Si and Ge having the same family element as Si SOLUTION: The roughness of an interface between the distortion applying layer of SiGe and the distortion semiconductor layer of Si deposited thereon, or an interface between the distortion semiconductor layer of Si and the gate insulating layer on it are reduced to an appropriate value, and MOSFET is formed on the distortion semiconductor layer of Si

Abstract: The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.