MOSFET

Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.