Moore machine

Abstract: A fail-safe sequential machine is one that produces safe-side output when failures occur in the machine. This paper presents a new method of realization of fail-safe sequential machines under the following assumptions: 1) failure is caused by a single fault of element in the machine, 2) output of faulty element is stuck at one or zero, and 3) input does not malfunction.

Abstract: A method and apparatus which automatically extract finite state machine circuits from a circuit design. Typically, the circuit design is specified by a hardware description language which is compiled to a level of description which shows logic and interconnections in the circuit. A circuit region which includes a register is automatically defined from this description. The circuit region is defined as the register and the group of logic gates within a feedback path from the output of the register to the input of the register. The circuit region is analyzed to define a finite state machine. For each finite state machine, the next state function of the state machine is determined. The next state function is derived by determining a next state from a current state of the state machine and a set of possible input values to the state machine. A symbolic representation of the state machine may be generated from the next state function, and state machine may be optimized and/or debugged in its symbolic representation. The state machine may then be recompiled from the symbolic representation. In one example, the state machine may be recompiled into a target architecture.

Abstract: There has been a lot of interest in the use of discrete-time recurrent neural nets (DTRNN) to learn finite-state tasks, with interesting results regarding the induction of simple finite-state machines from input--output strings. Parallel work has studied the computational power of DTRNN in connection with finite-state computation. This article describes a simple strategy to devise stable encodings of finite-state machines in computationally capable discrete-time recurrent neural architectures with sigmoid units and gives a detailed presentation on how this strategy may be applied to encode a general class of finite-state machines in a variety of commonly used first- and second-order recurrent neural networks. Unlike previous work that either imposed some restrictions to state values or used a detailed analysis based on fixed-point attractors, our approach applies to any positive, bounded, strictly growing, continuous activation function and uses simple bounding criteria based on a study of the conditions under which a proposed encoding scheme guarantees that the DTRNN is actually behaving as a finite-state machine.

Abstract: We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized "burst-mode" multiple-input change asynchronous designs, but also allows the automatic synthesis of any synchronous Moore machine using only basic gates (and not state-holding elements). Moreover, the synthesis method covers many circuit styles in the range between burst-mode and fully synchronous. We can easily specify and synthesize sequential circuits which change state on both rising and falling clock edges, have multiple-phase clocks, etc., and mixed synchronous/asynchronous designs, subject only to setup and hold-time constraints. To demonstrate the effectiveness of the design style and the synthesis tool, we present a modified version of a previously published large practical controller design - the SCSI data transfer controller redesigned to improve performance and to eliminate preprocessing circuit for converting "level-sensitive" signals to "edge-sensitive" signals, often a cumbersome manual design process, by interfacing directly with "level-sensitive" signals.