Abstract: Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method.

Abstract: A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

Abstract: A multiphase multilevel voltage source inverter (VSI) offers excellent advantages over the traditional three-phase counterparts. Low-order harmonic components with reduced switching losses, lower common-mode voltage (CMV), and the optimum use of dc-link voltage constitute the critical performance indicators for high-efficiency VSI evaluation. Various approaches for carrier-based pulsewidth modulation (CPWM) generation are available in the literature along with space vector pulsewidth modulation (SVPWM) techniques. Comparative analysis shows that the majority of SVPWM strategies have enormous potential than CPWM to achieve the aforementioned performance indices. The main objective of this article is to provide a common platform for the selection of available five-phase VSIs for various industrial applications. For this, a comparative study is carried out to examine in various aspects like CMV, voltage and current total harmonic distortion (THD), switching, conduction losses, and efficiency under the steady-state and dynamic loading conditions over a wide range of the modulation index. It is observed that the five-phase three-level neutral-point-clamped (NPC) VSI has better performance than the five-phase two-level VSI. Experimental results are provided to verify the performance indices of both topologies at steady-state and dynamic conditions.

Abstract: This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n -level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme.

Abstract: Medium-voltage high-speed drive is promising in applications, such as the centrifugal compressors and electrified transportation. However, it raises lots of design challenges for the converters, which drive the motors. A SiC and Si hybrid ANPC converter is developed to address these challenges. In this article, the essence of this hybrid structure is investigated to clearly show the derivation process of the hybrid active neutral-point-clamped (ANPC) converter and inspire future research on these hybrid topologies. A dedicated space vector modulation (SVM) scheme is proposed for the hybrid ANPC converter, which enables the three-phase hybrid ANPC converter operating with SiC mosfet s in high frequency and Si IGBTs in fundamental frequency. A neutral point (NP) voltage balancing scheme is added to the SVM scheme to balance the NP voltage imbalance under low-frequency modulation index. All these efforts make the hybrid ANPC converter become a high power density and fairly low-cost solution. A 400 Hz fundamental frequency, 3.6 kHz switching frequency, medium-voltage high-speed drive system is assumed and tested by the scaled-down experimental results. The effectiveness of the proposed SVM and NP voltage balancing method have both been verified.

Abstract: This paper investigates the performance optimization of optically pumped magnetometers under zero-field parametric modulation. Based on the analytical solutions of the Bloch equation, both longitudinal and transverse modulations are studied experimentally. To estimate the nonuniform polarization distribution of alkali-metal atoms in the vapor cell, an average pumping rate model is proposed. Furthermore, the accuracy of this model and the measurement of the transverse relaxation rate are verified via the agreement between experimental and theoretical values. The results indicate that optimal performance can be achieved by employing a suitable modulation field, the selection of which is related to the modulation index $u$ in the Bessel series and the pump-light intensity. Although both operating modes show similar responses to weak magnetic fields, their effects on pump-light intensity are different due to the means of detecting atomic polarization. An optimal value of the pump-light intensity on the response strength exists in longitudinal modulation. However, with regard to transverse modulation, the sensitivity under weak pump-light intensity is better. This research has far-reaching significance for cases when the parametric modulation is manipulated.

Abstract: High-power traction systems usually operate under low-switching-frequency conditions to avoid high switching losses. Synchronized space vector pulsewidth modulation (synchronized SVPWM) is an effective modulation method in low-switching-frequency modulation for its balanced harmonic performance and implementation complexity. A number of pulse pattern patterns in synchronized SVPWM are developed for application with different frequency ratios. In this article, the authors systematically analyzed the performance of pulse pattern and developed a harmonic-reduced pulse pattern selection strategy considering the influence of the modulation index. An implementation of synchronization SVPWM with strong universality is proposed, which includes a phase-locked loop (PLL) based synchronization method and pulse pattern transition strategy. The transition strategy can handle the transition for special-vector-sequence pulse patterns and over-modulation operation. The harmonic-reduced synchronized SVPWM strategy and its implementation are verified through simulations and experiments.

Abstract: A novel nine-level inverter topology for low-voltage applications is proposed in this paper. Each phase of the inverter is composed of a T-type three‐level cell and an active neutral point clamp three‐level cell. The operation principles and current conduction paths are analyzed in detail and phase-disposition sinusoidal pulsewidth modulation is used to balance voltages of flying capacitors and neutral point. The mathematical relationship between the capacitance and the desired ripple in the inverter output is established to select the intermediate capacitance value. Compared with other nine-level inverters suitable for low-voltage applications, the proposed inverter has advantages in a number of gate drivers, a number of dc sources, and efficiency. Simulation and experimental results under different settings of modulation index, power factor, output frequency, and load are presented to verify the effectiveness and performances of the proposed inverter.

Abstract: In this paper, a new optimal pulsewidth modulation (PWM) scheme for a three-level quasi-switched boost T-type inverter (TL qSBT2I) under normal and failure modes is proposed. The proposed method reveals its semiconductor fault tolerance capability in open-circuit fault condition situations as described in this paper. The PWM control algorithm for the fault-tolerant qSBT2I is implemented by selecting appropriate values for the modulation index, shoot-through (ST) duty cycle, and duty cycles of two additional switches. The steady-state analysis and operating principles of the fault-tolerant qSBT2I are presented. A laboratory prototype was built to verify the operating principles of the qSBT2I with the proposed modulation scheme before and after fault conditions.

Abstract: The phase-shifted-carrier (PSC) technique is preferred for multilevel converters in medium-voltage applications with low submodule (SM) number. This technique can elevate the equivalent switching frequency resulting in low total harmonic distortions. However, for half-/full-bridge hybrid modular multilevel converter (MMC) with boosted modulation index, the conventional PSC method is invalid due to the asymmetric voltage reference wave. The SM capacitor voltages deviate from the rated value and harmonics below equivalent switching frequency appear in the arm and equivalent ac voltages. This paper introduces an improved PSC technique with a capacitor sorting algorithm to overcome this problem. The negative part of the reference wave is turned over and then multiplied by a correction factor. The angular displacement for triangular carriers between the upper and lower arms is determined by the parity of the half-bridge number per arm. With the proposed method, the capacitor voltages are balanced and the ac voltage of MMC has the lowest harmonic distortion. Double-Fourier analysis for the proposed technique is carried out, and harmonic characteristics are revealed. The experimental results validate the correctness and feasibility of the improved PSC technique for hybrid MMC with boosted modulation index and asymmetric reference wave.

Abstract: This article presents an optimal carrier-based voltage balancing scheme for three-phase three-level converters. The proposed scheme utilizes two available degrees of freedom, i.e., zero-sequence signal injection and virtual zero-level modulation (VZM), to eliminate the low-frequency neutral-point voltage oscillation. It is universally effective over the full power factor and modulation index range and easy to implement in digital controllers. The hybrid algorithm combines the merits of both approaches, which offers the optimal performance regarding controllability, switching device power losses, and output harmonics. The main drawbacks of VZM, i.e., the increased switching loss and high-frequency harmonics due to additional switching transitions, have been minimized in the proposed scheme. The performance of the proposed scheme is evaluated through simulation and experiment.

Abstract: A unified selective harmonic elimination (SHE) control for four-level hybrid-clamped (4L-HC) inverters is presented in this article. With this unified strategy, all four-level switching patterns and the corresponding switching angles can be obtained simultaneously by solving one group of unified four-level SHE equations. Therefore, the optimal switching pattern of each modulation index with the designed optimization goal can be evaluated, and the best overall output performance is achieved. In order to ensure the proper operation of the 4L-HC inverter, the voltages across the three-phase flying capacitors and three dc-link capacitors must be controlled and balanced at one-third of the dc-link voltage. The proposed voltage control method is based on redundant switching states and introducing a slight variation to the precalculated switching angles, which extends or limits the conduction time of capacitors depending on voltage deviation and current direction. The effect of switching angle variations on the harmonic performance is also studied. Simulation and experimental results are presented to confirm the validity of the unified model and the proposed voltage-balancing strategy. Comparisons with phase-shifted pulsewidth modulation (PWM) are also presented to demonstrate that the implemented SHE-PWM could significantly reduce the switching frequency while keeping the capacitor voltages well balanced within the expected band limits.

Abstract: Full time-domain analysis of the impact of third-harmonic injection (THI) on the output phase voltage waveform of a two-level voltage source inverter is presented, and the total harmonic distortion (THD) performance of different pulsewidth modulation (PWM) methods is provided. Two well-known third harmonic injection PWM (THIPWM) schemes are adopted from the literature: THIPWM6 and THIPWM4, where the THI amplitude is one-sixth and one-fourth the amplitude of the sine-wave, respectively. In this article, three analysis-derived developments are provided. Global optimal THIPWM ensures minimum THD in all linear region, unlike other THIPWM schemes. A unique THI-level is selected for each modulation index from the proposed curve or the compacted lookup table. The best suboptimal THIPWM method is provided that employs a linear injection applied over the linear modulation. To achieve better THD performance and to satisfy different operation criteria, several suboptimal THIPWM methods are proposed. Comparisons between these schemes must define performance indices, and this is carried out using various objective functions, such as the sum of squared error and area under the curve. The impact on extending the linear region is also presented. This study examines when THIPWM is useful and which injection level is best. Experimental verifications support the presented analysis.

Abstract: The quasi-impedance source inverters/quasi-Z source inverters (Q-ZSIs) have shown improvement to overwhelmed shortcomings of regular voltage-source inverters (VSIs) and current-source inverters (CSIs) in terms of efficiency and buck-boost type operations. The Q-ZSIs encapsulated several significant merits against conventional ZSIs, i.e., realized buck/boost, inversion and power conditioning in a single power stage with improved reliability. The conventional inverters have two major problems; voltage harmonics and boosting capability, which make it impossible to prefer for renewable generation and general-purpose applications such as drive acceleration. This work has proposed a Q-ZSI with five-level six switches coupled inverter. The proposed Q-ZSI has the merits of operation, reduced passive components, higher voltage boosting capability and high efficiency. The modified space vector pulse width modulation (PWM) developed to achieve the desired control on the impedance network and inverter switching states. The proposed PWM integrates the boosting and regular inverter switching state within one sampling period. The PWM has merits such as reduction of coupled inductor size, total harmonic reduction with enhancing of the fundamental voltage profile. In comparison with other multilevel inverters (MLI), it utilizes only half of the power switch and a lower modulation index to attain higher voltage gain. The proposed inverter dealt with photovoltaic (PV) system for the stand-alone load. The proposed boost inverter topology, operating performance and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for the stand-alone and grid-connected system.

Abstract: Due to the presence of full-bridge submodules (FBSMs), hybrid modular multilevel converters (HMMCs) consisting of FBSMs and half-bridge submodules (HBSMs) can work under the over-modulation conditions, which means that half of the dc voltage is less than the magnitude of the ac voltage. However, because of the different charging and discharging characteristics of FBSMs and HBSMs under over-modulation conditions, capacitor voltages imbalance may occur if the modulation index exceeds a specific limit. To address this issue, this article first investigates the principles of HMMCs and the energy balance mechanism between the two types of submodules. Based on the theoretical analysis, a negative-sequence second-order circulating current injection method is proposed to keep the capacitor voltage balanced under over-modulation conditions. Finally, the proposed method is validated by both simulation and experimental results.

Abstract: It is necessary to suppress the emission level of conducted electromagnetic interference (EMI) for the power electronics converters, and the variable switching frequency pulsewidth modulation (VSFPWM) is an alternative approach to reduce conducted EMI without adding bulky passive components. However, the experimental results indicate that many obvious EMI spikes in spectrum remain so that the conducted EMI reduction for VSFPWM is limited. In order to eliminate the EMI spikes in spectrum, this article first investigates the cause of the EMI spikes for VSFPWM, and the analysis results show that the nonuniform distribution of switching frequency is the primary reason. Then, a novel PWM strategy called uniform distribution PWM (UDPWM) is proposed to eliminate the EMI spikes and to further reduce conducted EMI. The design of a UDPWM is based on the uniform distribution of switching frequency and the principle of less switching loss. Moreover, the analytical formula of switching frequency is also deduced in detail, which adopts fixed variation range of switching frequency whatever the modulation index is. Finally, the experiments are carried out to validate the effectiveness of the UDPWM in reducing conducted EMI and switching loss. The UDPWM can approximately reduce conducted EMI by 20 dB compared with the conventional constant switching frequency PWM, and all obvious spikes in the spectrum are eliminated compared with VSFPWM.

Abstract: The ability of current-derivative based speed and position estimation of IPMSMs over a full speed range has recently been demonstrated. However, at high-speeds, the modulation index becomes limited because the extension of the zero-voltage vectors and current waveforms become distorted. This article proposes a hybrid position and speed estimation technique which uses current derivatives at the first active-voltage vector during each pulsewidth modulation (PWM) switching period for enhancing the performance of a sliding mode observer at low and very low speeds. This article presents the theoretical analysis and experimental evaluation of the proposed sensorless method for an IPMSM over a full speed range from zero to rated speed. The experimental results have shown a significant improvement in speed and position estimation accuracy at low speeds and a considerable reduction of the current distortion over the full speed range, compared to the existing fundamental PWM excitation sensorless control methods.

Abstract: The aim of this paper is to use Space Vector Pulse Width Modulation (SVPWM) technique and Sinusoidal Pulse Width Modulation (SPWM) technique to mathematically prove and compare the DC bus utilization for a Neutral Point Clamped (NPC) three level Inverter. The comparative analysis between SVPWM and SPWM is made in the linear region of Modulation Index. The analogous relationship between the modulation indices for SPWM and SVPWM is presented here. Besides this it is also shown that Total Harmonic Distortion (THD) is lower for SVPWM technique than SPWM technique. The results are simulated for a NPC three level Inverter feeding RL load with the help of MATLAB/SIMULINK.

Abstract: In a single-stage buck-boost quasi-switched boost inverter (qSBI), the shoot-through state insertion causes high amplitude common-mode voltage. Consequently, the qSBI becomes less attractive in transformerless photovoltaic (PV) systems. In this paper, a novel space vector pulse-width modulation for a modified qSBI is introduced to reduce the magnitude of common-mode voltage and push the modulation index up to 1. By properly choosing the shoot-through interval time, shoot-through states are considered to be inserted for boosting voltage and also reducing the THD value of the output voltage. The mathematical analysis and operating principles of the converter are discussed and verified through PSIM simulations. Finally, an experimental prototype is validated based on a TMS320F28335 DSP microcontroller and a DE0-Nano FPGA digital control platform.

Abstract: Numerous Z-source three-phase inverters are developed for realizing higher voltage gain which are suitable to use in hybrid electric vehicle to drive the electric machine. However, higher voltage and current stress of the passive elements and semiconductor devices are the major limitations of the reported Z-source inverters. In this article, a new quasi-switched boost three-phase inverter is proposed which has the following features: 1) very low continuous input current; 2) reduced voltage stress; 3) reduced current stress; 4) shoot through immunity; 5) single stage voltage conversion from dc to ac; and 6) improved output voltage quality by utilizing higher modulation index. The operation, steady-state analysis, and design guidelines for the proposed converter are discussed in detail. To prove the feasibility of the proposed inverter, a comparative analysis is also presented with the state-of-the-art converters. An experimental setup is designed on printed circuit board and tested for 400 W power rating.

Abstract: A cascaded H-bridge (CHB) converter has been widely used and researched in industry since it is suitable for the operation under both normal and fault conditions. This paper proposes a novel pulsewidth modulation strategy based on state transition for CHB inverter with unbalanced dc sources to achieve high-quality line-to-line output voltages and maximize the linear modulation range. In this modulation strategy, the duration time of each switching state will be modified directly through the correction value. Ranges of correction value are derived by analyzing the modulation index limitation. Then, a proper correction value is added into duration times to transform the switching states and extend modulation index to the maximum value. Meanwhile, balanced ac currents can be obtained under unbalanced dc sources condition, even under larger unbalanced coefficients. Furthermore, a three-phase power control algorithm is introduced to achieve the balanced distribution of three-phase power. Compared with the traditional zero-sequence voltage injection method, the proposed strategy is more convenient and effective theoretically, and it can be applied to the higher level CHB converter. The advantage and effectiveness of the proposed strategy are verified by simulation and experimental results.

Abstract: The application of quasi-Z source inverters (qZSI) for renewable energy sources has been presented as an attractive solution. This kind of inverters perform power conversion in a single stage with buck/boost capability and improved reliability compared to the conventional voltage source inverter. This paper focuses on the application of qZSI to a large-scale grid-connected photovoltaic (PV) system. The active and reactive powers are controlled using a version of the space vector modulation technique adapted to qZSI that allows a high modulation index. Furthermore, the sizing of the impedance components and the filter are described considering commercial values. Simulations are performed under a voltage sag and load variation on the grid, in order to verify the right design and performance of system and control methods. The results confirm the effectiveness of the proposed model and the control techniques applied to the large-scale grid-connected qZSI-based PV power plant.

Abstract: With conventional pulsewidth modulation (PWM) strategies, the switches of a three-level T-type neutral-point-clamped (T-NPC) inverter are not equally utilized at modulation indices lower than 0.5, limiting the inverter power throughput. The inner switches incur more losses than the outer switches. This article investigates a series of space-vector-based discontinuous PWM (DPWM) templates for modulation indices lower than 0.5. The templates relocate the phase current from the inner to the outer switches of a T-NPC inverter. Using them, the device losses are reduced and get redistributed more equally among the inner and outer switches, enabling a higher inverter output current or switching frequency. Confirmatory simulation and experimental results are provided to demonstrate the potential of the three-level DPWM templates in comparison to the conventional PWM templates.

Abstract: In this paper, a novel filter structure to suppress circulating currents is proposed based on the sequence of pulsewidth modulation voltage harmonics for high-power interleaved motor-drive systems. The sideband harmonics can be divided into positive-, negative-, and zero-sequence components. Through 120° interleaving among three paralleled inverters, a majority of positive- and negative-sequence harmonics are phase shifted. By these phase shifts, the differential-mode circulating currents between the paralleled ac–dc converters can be suppressed with the proposed filters, which have an identical structure to the three-phase common-mode chokes. Such a structure highly benefits the design and manufacturability for high-power applications where a choice of magnetic-core shapes is limited. Compared to coupled inductors (CIs) with cyclic-cascade or monolithic configurations, the number of magnetic cores can be reduced by one-third. Peak flux-linkages of the proposed filters and the conventional CIs were compared to estimate the size reduction in case of flux-limited designs. Considering the whole modulation index range, which may be required in the motor-drive systems, the maximum flux-linkage can be reduced by 50%. Prototype filters are built and showed a 33% reduction in weight and size compared to the conventional CIs. The validity of the proposed filter is verified through the simulation and a small-scale experiment.

Abstract: This paper presents two novel algorithms for the calculation of semiconductor losses of a three-phase quasi-Z-source inverter (qZSI). The conduction and switching losses are calculated based on the output current-voltage characteristics and switching characteristics, respectively, which are provided by the semiconductor device manufacturer. The considered inverter has been operated in a stand-alone operation mode, whereby the sinusoidal pulse width modulation (SPWM) with injected 3rd harmonic has been implemented. The proposed algorithms calculate the losses of the insulated gate bipolar transistors (IGBTs) and the free-wheeling diodes in the inverter bridge, as well as the losses of the impedance network diode. The first considered algorithm requires the mean value of the inverter input voltage, the mean value of the impedance network inductor current, the peak value of the phase current, the modulation index, the duty cycle, and the phase angle between the fundamental output phase current and voltage. Its implementation is feasible only for the Z-source-related topologies with the SPWM. The second considered algorithm requires the instantaneous values of the inverter input voltage, the impedance network diode current, the impedance network inductor current, the phase current, and the duty cycle. However, it does not impose any limitations regarding the inverter topology or switching modulation strategy. The semiconductor losses calculated by the proposed algorithms were compared with the experimentally determined losses. Based on the comparison, the correction factor for the IGBT switching energies was determined so the errors of both the algorithms were reduced to less than 12%.

Abstract: We performed two experiments to ascertain whether vocal selftraining improves speech clarity, particularly when the feedback speech is degraded by a hearing impairment simulator. Speech sounds before and after the training were recorded under noisy and quiet conditions and their speech clarity was evaluated by subjective listening tests using Scheffe’s paired comparison. We also analyzed the auditory modulation features to derive an index to explain the subjective clarity scores. The auditory modulation index highly correlated with subjective scores and seems a good candidate for predicting speech clarity.

Abstract: Multilevel inverters are finding wide application in electric drives, traction, flexible AC transmission systems (FACTS) and renewable energy systems A cascaded H-bridge type multilevel inverter (CHBMLI) produces a near sinusoidal output voltage with lower switching stress and a higher conversion efficiency than the other types of MLIs The Selective Harmonic Elimination (SHE) strategy is used to eliminate lower-order harmonic profiles and to regulate the fundamental component in the output voltage SHE has the advantages of low switching frequency, low switching losses and low stress In this paper, the modulation index and input voltage values are also considered as optimization variables along with the conventional switching angles to analyze the performance improvement in selective harmonic elimination Heterogeneous Comprehensive Learning Particle Swarm Optimization (HCLPSO) and Gravitational Search Algorithm (GSA) algorithms are used to find the optimal switching angles, modulation index and input voltage source values for minimizing the lower-order harmonics present in the output voltage of seven-level and eleven-level CHBMLIs, while maintaining the fundamental component of the output voltage The results obtained from MATLAB simulations and an experimental setup clearly indicate that the proposed HCLPSO-based multilevel inverter provides better performance when compared with GSA, firefly and Differential Search Algorithm (DSA)-based MLIs