Topic
Model-specific register
About: Model-specific register is a research topic. Over the lifetime, 10 publications have been published within this topic receiving 107 citations.
Papers
Patent•
17 Jul 1997TL;DR: The model specific instruction redefinition register (MSR) as discussed by the authors is a model specific register defined by the x86 microprocessor architecture, which can be used to define new instructions without consuming opcode encodings.
Abstract: A microprocessor employs an instruction redefinition register which programmably redefines the operation performed by one or more instructions. Instructions may be added to the instruction set executed by the microprocessor without consuming opcode encodings. One or more new instructions may be mapped to an opcode assigned to a redefinable instruction (e.g. a seldom-used instruction selected during the design of the microprocessor to be redefinable to one or more of the added instructions). A particular application program may select the architecturally defined operation corresponding to the redefinable instruction or one of the operations corresponding to the new operations by coding the instruction redefinition register. In one particular embodiment, the instruction redefinition register is a model specific register (MSR) as defined by the x86 microprocessor architecture. A frequently-used instruction may also be selected as a redefinable instruction for purposes of expanding the microprocessor resources available as operands of that instruction.
31 citations
Patent•
18 Apr 2003TL;DR: In this article, a model specific register of a processor having a normal execution mode and a secure execution mode may be used to store processor state and mode information in the model-specific register.
Abstract: A method of controlling access to a model specific register of a microprocessor. A method of controlling access to a model specific register of a processor having a normal execution mode and a secure execution mode may include storing processor state and mode information in the model specific register. Further, the method may include protection logic allowing a software invoked write access to modify the information within the model specific register during the normal execution mode. The method may further include security logic selectively inhibiting the software invoked write access during the secure execution mode.
30 citations
Patent•
7 Apr 2004TL;DR: In this paper, a model specific register logic that facilitates manipulating model specific registers so that bits that are irrelevant to a processor simulation are not set for the processor simulation is described, and a data store that is configured to store significance vectors that encode information about (irrelevant model-specific register bits.
Abstract: Systems, methodologies, media, and other embodiments associated with manipulating model specific registers are described. One exemplary system embodiment includes a model specific register logic that facilitates manipulating a model specific register so that bits that are irrelevant to a processor simulation are not set for the processor simulation. The exemplary system may also include a data store that is configured to store significance vectors that encode information about (ir)relevant model specific register bits and that facilitate the model specific register logic manipulating a model specific register to a desired initial state.
20 citations
Patent•
21 Dec 2013
TL;DR: In this paper, a decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the secondMSR value responsive to the swap instruction, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.
Abstract: Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.
10 citations
Patent•
24 Jan 2005TL;DR: In this paper, a method for stalling execution of a model specific register write function to prevent disabling of the no-execute processor feature is proposed. But the method is limited to a single processor.
Abstract: A method includes stalling execution of a model specific register write function to write to a model specific register of a processor having a no-execute processor feature enabled, determining that the model specific register is a no-execute model specific register of the processor, and determining whether a no-execute field in the no-execute model specific register is being altered. Upon a determination that the no-execute field is being altered, the method further includes taking protective action to prevent disabling of the no-execute processor feature.
5 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2017 | 2 |
| 2016 | 1 |
| 2015 | 1 |
| 2013 | 1 |
| 2011 | 1 |
| 2005 | 1 |