Millicode

Abstract: A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage "milli-instructions" and an interpretive execution "milli-mode". Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implement complex functions. One milli-instruction called the DRAIN INSTRUCTION PIPELINE (DIP) causes the pipeline to drain selectively so the milli-programmer determines when and and what type of pipeline drain to perform. A DRAIN INSTRUCTION PIPELINE causes suspension of decoding until a selected event occurs. This DIP instruction includes options for suspending decoding until one of the following events have occurred: 1. all conceptually previous macro-instructions have completed; 2. all conceptually previous instructions have completed; 3. all store requests have reached the point where no exceptions would occur, but the actual store may not have completed; 4. all conceptually previous stores from all conceptually previous units-of-operation have competed (serialize); or 5. invalidate instruction buffers and fetch the next sequential macro-instructions.

Abstract: An alternate instruction architecture which uses the preexisting dataflow and hardware controlled execution units of an otherwise conventional pipelined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These milli-mode instructions augment the standard "user visible" architected instruction set (which in the preferred embodiment is the System 390 instruction set). Millicode routines can intermingle the milli-mode only instructions with standard system instructions to implement complex functions. The set of instructions available in milli-mode can be considered to be an alternate architecture that the processor can execute. The millicode and standard system architectures each have there own set of architected registers. However, these registers are dynamically taken from and returned to a common physical register pool under control of a register management system. Provision is also made for communication between the two architectures such that data in the milli-registers and the standard architected registers (such as GPRs) can be exchanged. A set of register operand registers is provided to enable explicit updates of general purpose registers from millicoded routines. Both milli-instructions and standard architecture instructions can be present in the pipeline simultaneously. Provision is thus also made for performing a controlled pipeline reset of the facilities manipulated by the two types of architectures.

Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.

Abstract: The S/390® Parallel Enterprise Server Generation 4 processor is an implementation of the IBM ESA/390™ architecture on a single custom CMOS chip. It was designed on a blank slate after consideration of remapping either a prior CMOS design or a prior bipolar design. It uses a straightforward pipeline both to achieve a fast cycle time and to speed the design cycle. The complex instructions are implemented using highly privileged subroutines called millicode. To achieve high data integrity while maintaining a high clock frequency, the chip contains duplicate I- and E-units which perform the same operations each cycle and have their results compared.