Miller effect

Abstract: The Class E amplifier requires exact shunt capacitance to achieve optimum operation. Most Class E amplifiers are usually constructed by adding an external capacitor to the output capacitance of the power transistor in order to obtain the total required shunt capacitance. The output capacitance of the power transistor is nonlinear and the external capacitance is linear. Therefore, neither design equations for linear shunt capacitance nor the design equations for nonlinear shunt capacitance can be used in most designs, especially when the two are comparable. This paper presents an analysis and a design procedure for the Class E amplifier with a shunt capacitance composed of both a transistor nonlinear output capacitance and a linear external capacitance for the duty cycle D=0.5. Because the design equations do not have analytical forms, this paper provides a table and figures, which show results of numerical analysis. The Class E amplifier can be designed using these table and figures. A design example is given to illustrate the design procedure. Simulation results of the example circuit with PSpice and experimental results are presented to verify the theoretical results.

Abstract: Comparison of various parameters of the class-E amplifier with nonlinear and linear shunt capacitance is given. A concept of an equivalent linear shunt capacitance is introduced. The following parameters are compared for the amplifiers with nonlinear and linear shunt capacitance at the duty cycle D=0.5: series reactance, peak switch voltage, and power capability. A design procedure for the class-E amplifier with a nonlinear shunt capacitance is presented. Simulation of the designed class-E amplifier is performed to verify the design equations that ensure zero-voltage-switching operation.

Abstract: A capacitance measuring apparatus is provided, for example for measuring variations in pixel capacitance of an active matrix liquid crystal display to provide a “touch screen” function. The apparatus comprises a capacitor network having a plurality of states presenting different capacitances. A sense amplifier compares a capacitance to be measured with the capacitance of the network and a comparator supplies an output indicating whether the capacitance to be measured is larger or smaller than the capacitance of the network. A control circuit causes the network to switch through its states and monitors the output of the comparator so as to select the state of the network presenting a capacitance adjacent the capacitance to be measured. The digital measurement corresponding to the capacitance presented by the network is supplied to an output and provides a measure of the capacitance to be measured.

Abstract: Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.