Microsecond Bus

Abstract: A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus.

Abstract: A microsecond bus master 20 has chip select outputs CS1, CS2, each connected to more than one slave device IC16. The slaves have configuration pins, which are connected to ground or to a supply voltage. When the master sends a data frame to the slaves on the data bus 10, the chip select signal determines which slaves accept bits from the data frame. The configuration pins determine which bits from the frame each slave accepts. The slave devices may be H-bridge circuits which drive a pair of DC motors, requiring three input bits per motor. In this case, if both configuration pins are connected to ground, the slave device may use the first six bits of the data frame to control the motors. Other settings of the configuration pins allow other blocks of six bits to be used.

Abstract: The invention relates to a circuit assembly (ASIC) having a microsecond bus interface (MSCII Interface) for communicating with a microprocessor (muC) The microsecond bus interface has at least connections for data to be received (M_SDI), for data to be sent (M_SDO), and for an external clock signal (M_CLK) The circuit assembly also has a divider circuit (Divider), which divides the frequency of the external clock signal (M_CLK) in order to control the data transmission from the circuit assembly to a microprocessor (muC), and a state machine, which is designed to set a flag during transmission of data from the circuit assembly to a microprocessor (muC) and, when data requiring a response are received from the microprocessor while the flag is set, to suppress the transmission of the response to the microprocessor (muC)