MBus

Abstract: The reliability of memory systems that are exposed to soft errors has been studied in the past with the aim of deriving the mean time to failure (MTTF) and the probability of failing in a given time interval. On those studies, the soft errors were considered to arrive following a Poissonian basis and they were assumed to be single uncorrelated events (each event causes only one soft error). Recent studies suggest that multiple bit upsets (MBUs) are a significant part of the error events in advanced memory technologies and that they will continue to grow in the next technology nodes. The errors in an MBU are normally caused by the same physical event and therefore affect memory cells that are close together. This poses a major problem to memories that are protected with per-word single error correction codes, as an MBU is likely to affect two or more bits in the same word, causing an uncorrectable error. To avoid that problem, interleaving is used to ensure that cells that are physically close together belong to different logical words, so that the errors in an MBU are distributed over a number of words each suffering only one error. Although some works have been done that characterize memories under radiation tests, no mathematical model of the effect of MBUs on the reliability of a memory has been proposed in the literature, to the best of the authors' knowledge. Therefore, in this paper, the reliability of memories suffering MBUs is analyzed in detail. The fundamental result from that analysis is that the MTTF of a memory exposed to MBUs can be approximated using the existing results for single event upsets by adjusting the error arrival rate.

Abstract: The local Message Bus (Mbus) is a light-weight message-oriented coordination protocol for group communication between application components. The Mbus provides automatic location of communication peers, subject based addressing, reliable message transfer and different types of communication schemes. The protocol is layered on top of IP multicast and is specified for IPv4 and IPv6. The IP multicast scope is limited to link-local multicast. This document specifies the Mbus protocol, i.e., message syntax, addressing and transport mechanisms.

Abstract: As technology scaling increases embedded static random access memory bit-cell density, the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases. Traditionally, these errors have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling, however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this brief, a set of double adjacent error correction (DAEC) codes is modified to provide triple adjacent error correction for a cost of zero additional check-bits over the code's DAEC equivalent, yielding a 2.25 $\times$ reduction in bit-level soft error rate for a 22-nm MBU error channel model. MATLAB simulation and HDL synthesis results are included for standard 16- and 32-data-bit memory word sizes and compared against existing codes.

Abstract: The SuperSPARC microprocessor is a highly integrated, high-performance superscalar SPARC version 8 compatible microprocessor. The authors provide an overview of its internal operation and capabilities. The processor contains an integer unit, a double precision floating point unit, fully consistent instruction and data caches, a SPARC reference memory management unit and a dual-mode bus interface supporting either the SPARC standard MBUS or an interface optimized for connection to a companion second-level cache controller chip. The chip is constructed using Texas Instruments 0.8- mu triple-layer metal BiCMOS technology. >